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1. 发明授权

US08395441B1 Dynamic biasing circuit 有权
标题翻译：动态偏置电路
公开(公告)号：US08395441B1
公开(公告)日：2013-03-12
申请号：US13278414
申请日：2011-10-21
申请人： Rajavelu Thinakaran
发明人： Rajavelu Thinakaran
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/262
摘要： A dynamic biasing circuit includes a first input pair coupled to a second input pair, the first input pair including a first transistor and a second transistor with sources coupled to each other, and the second input pair comprising a third transistor and a fourth transistor with sources coupled to each other, the sources receiving a bias current. A first current mirror that generates an output current is coupled to the first input pair. A second current mirror is coupled to the first input pair and the second input pair. The second current mirror is configured to force the current to drop in the fourth transistor in response to sensing a current drop in the first transistor such that the bias current flows through the second and third transistors that boosts the output current.
摘要翻译：动态偏置电路包括耦合到第二输入对的第一输入对，所述第一输入对包括第一晶体管和第二晶体管，所述第一晶体管和第二晶体管具有彼此耦合的源极，所述第二输入对包括具有源极的第三晶体管和第四晶体管彼此耦合，源接收偏置电流。产生输出电流的第一电流镜被耦合到第一输入对。第二电流镜耦合到第一输入对和第二输入对。第二电流镜被配置为响应于感测第一晶体管中的电流降而迫使电流落在第四晶体管中，使得偏置电流流过提高输出电流的第二和第三晶体管。

2. 发明授权

US08198912B1 Driver circuit correction arm decoupling resistance in steady state mode 有权
标题翻译：驱动电路校正臂解耦电阻在稳态模式
公开(公告)号：US08198912B1
公开(公告)日：2012-06-12
申请号：US12979336
申请日：2010-12-28
申请人： Rajavelu Thinakaran , Ashwin Ramachandran
发明人： Rajavelu Thinakaran , Ashwin Ramachandran
IPC分类号： H03K17/16
CPC分类号： H03K19/018571 , H03K19/01707 , H03K19/018585 , H03K19/018592 , H04L25/03834
摘要： A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and is operable, in pre-emphasis intervals as well as steady-state intervals, to connect a first impedance between an output terminal of the driver circuit and a constant reference potential. The correction arm is operable to connect a correction impedance in parallel with the first impedance in pre-emphasis intervals, and to decouple the correction impedance from the first impedance in steady-state intervals. The parallel connection of the first impedance and the correction impedance in pre-emphasis intervals increases the voltage level of the output signal of the driver circuit in pre-emphasis intervals. The use of the correction arm compensates for the effect of parasitic capacitance at one or more nodes of the driver circuit, thereby reducing the settling time of the output signal and enabling high-speed operation.
摘要翻译：实施支持预加重的电压模式驱动电路，以包括驱动器臂和校正臂。驱动器臂接收输入信号，并且可在预加重间隔以及稳态间隔中操作，以连接驱动电路的输出端和恒定参考电位之间的第一阻抗。校正臂可操作以在预加重间隔中与第一阻抗平行地连接校正阻抗，并且在稳态间隔中将校正阻抗与第一阻抗分离。在预加重间隔中，第一阻抗和校正阻抗的并联连接以预加重间隔增加驱动器电路的输出信号的电压电平。校正臂的使用补偿了驱动器电路的一个或多个节点处的寄生电容的影响，从而减小了输出信号的建立时间并实现了高速操作。

3. 发明授权

US08415986B2 Voltage-mode driver with pre-emphasis 有权
标题翻译：电压模式驱动器，预加重
公开(公告)号：US08415986B2
公开(公告)日：2013-04-09
申请号：US12979337
申请日：2010-12-28
申请人： Sumantra Seth , Rajavelu Thinakaran
发明人： Sumantra Seth , Rajavelu Thinakaran
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018521 , H04L25/0272 , H04L25/0278 , H04L25/028 , H04L25/03343
摘要： A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.
摘要翻译：支持预加重的电压模式驱动电路包括多个电阻，多个晶体管用作开关。操作晶体管的控制信号表示到驱动器电路的输入信号的逻辑电平。为了产生预加重输出，晶体管被操作以在驱动器的输出端子和对应的恒定参考电位之间连接电阻器的并联布置。为了在稳态下产生输出，晶体管被操作以连接驱动器的输出端上的一些电阻，从而降低输出电压。通过适当选择电阻器的电阻值来获得驱动器的期望的输出阻抗和期望的预加重电平。在稳态下，司机的电流消耗比预加重模式要小。

4. 发明申请

US20120161816A1 VOLTAGE-MODE DRIVER WITH PRE-EMPHASIS 有权
标题翻译：电压模式驱动器与前瞻性
公开(公告)号：US20120161816A1
公开(公告)日：2012-06-28
申请号：US12979337
申请日：2010-12-28
申请人： Sumantra Seth , Rajavelu Thinakaran
发明人： Sumantra Seth , Rajavelu Thinakaran
IPC分类号： H03K3/00
CPC分类号： H03K19/018521 , H04L25/0272 , H04L25/0278 , H04L25/028 , H04L25/03343
摘要： A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.
摘要翻译：支持预加重的电压模式驱动电路包括多个电阻，多个晶体管用作开关。操作晶体管的控制信号表示到驱动器电路的输入信号的逻辑电平。为了产生预加重输出，晶体管被操作以在驱动器的输出端子和对应的恒定参考电位之间连接电阻器的并联布置。为了在稳态下产生输出，晶体管被操作以连接驱动器的输出端上的一些电阻，从而降低输出电压。通过适当选择电阻器的电阻值来获得驱动器的期望的输出阻抗和期望的预加重电平。在稳态下，司机的电流消耗比预加重模式要小。

5. 发明申请

US20120161811A1 DRIVER CIRCUIT CORRECTION ARM DECOUPLING RESISTANCE IN STEADY STATE MODE 有权
标题翻译：驱动电路校正ARM在稳态模式下的解耦电阻
公开(公告)号：US20120161811A1
公开(公告)日：2012-06-28
申请号：US12979336
申请日：2010-12-28
申请人： Rajavelu Thinakaran , Ashwin Ramachandran
发明人： Rajavelu Thinakaran , Ashwin Ramachandran
IPC分类号： H03K19/003
CPC分类号： H03K19/018571 , H03K19/01707 , H03K19/018585 , H03K19/018592 , H04L25/03834
摘要： A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and is operable, in pre-emphasis intervals as well as steady-state intervals, to connect a first impedance between an output terminal of the driver circuit and a constant reference potential. The correction arm is operable to connect a correction impedance in parallel with the first impedance in pre-emphasis intervals, and to decouple the correction impedance from the first impedance in steady-state intervals. The parallel connection of the first impedance and the correction impedance in pre-emphasis intervals increases the voltage level of the output signal of the driver circuit in pre-emphasis intervals. The use of the correction arm compensates for the effect of parasitic capacitance at one or more nodes of the driver circuit, thereby reducing the settling time of the output signal and enabling high-speed operation.
摘要翻译：实施支持预加重的电压模式驱动电路，以包括驱动器臂和校正臂。驱动器臂接收输入信号，并且可在预加重间隔以及稳态间隔中操作，以连接驱动电路的输出端和恒定参考电位之间的第一阻抗。校正臂可操作以在预加重间隔中与第一阻抗平行地连接校正阻抗，并且在稳态间隔中将校正阻抗与第一阻抗分离。在预加重间隔中，第一阻抗和校正阻抗的并联连接以预加重间隔增加驱动器电路的输出信号的电压电平。校正臂的使用补偿了驱动器电路的一个或多个节点处的寄生电容的影响，从而减小了输出信号的建立时间并实现了高速操作。

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