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41. 发明授权

US08546913B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08546913B2
公开(公告)日：2013-10-01
申请号：US13064599
申请日：2011-04-01
申请人： Masatake Wada , Naoki Imakita
发明人： Masatake Wada , Naoki Imakita
IPC分类号： H01L27/118 , H01L23/52
CPC分类号： H01L23/5223 , H01L27/0207 , H01L27/0629 , H01L27/0805 , H01L27/11803 , H01L27/11898 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： A capacitance cell includes a substrate structure layer having pair diffusion regions, and an interconnect layer having pair of power supply lines. The capacitance cell also includes a capacitance composed of a first electrode, a dielectric member and a second electrode stacked together, and is formed in a frame shape and disposed in a space between the substrate structure layer and the interconnect layer so as to extend along an outer rim of the frame shape of a standard cell region in which a standard cell is arranged. The capacitance cell also includes a first substrate contact that electrically connects one of the pair of power supply lines to one of the diffusion regions externally of the standard cell region. The capacitance cell also includes a second substrate contact that electrically connects the other power supply line to the other diffusion region, externally of the standard cell region. The capacitance cell further includes a first capacitance contact electrically connecting the first electrode to the other diffusion region internally of the standard cell region, and a second capacitance contact electrically connecting the second electrode to the one power supply line internally of the standard cell region.
摘要翻译：电容单元包括具有对扩散区域的衬底结构层和具有一对电源线的互连层。电容单元还包括由第一电极，电介质构件和堆叠在一起的第二电极组成的电容，并且形成为框架形状，并且设置在基板结构层和互连层之间的空间中，以沿着设置有标准单元的标准单元区域的框架形状的外边缘。该电容单元还包括将该对电源线中的一个电连接到标准单元区域之外的扩散区域之一的第一基板接点。电容单元还包括将另一个电源线与标准单元区域外部的另一个扩散区域电连接的第二基板接点。电容单元还包括将第一电极与标准单元区域内部的另一个扩散区域电连接的第一电容接点和将第二电极与标准单元区域内部的一个电源线电连接的第二电容接触。

42. 发明授权

US08482001B2 Semiconductor device 有权
公开(公告)号：US08482001B2
公开(公告)日：2013-07-09
申请号：US12976582
申请日：2010-12-22
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： H01L27/12
CPC分类号： H01L27/1255 , G11C16/0433 , G11C16/26 , H01L21/84 , H01L27/108 , H01L27/10805 , H01L27/10873 , H01L27/11 , H01L27/1108 , H01L27/11517 , H01L27/11521 , H01L27/1156 , H01L27/11803 , H01L27/1225 , H01L29/24 , H01L29/7869
摘要： An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

43. 发明授权

US08476927B2 Programmable logic device 有权
公开(公告)号：US08476927B2
公开(公告)日：2013-07-02
申请号：US13453147
申请日：2012-04-23
申请人： Tatsuji Nishijima
发明人： Tatsuji Nishijima
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H01L27/11803 , H03K19/17728 , H03K19/1776 , H03K19/17772
摘要： An object of the present invention is to provide a programmable logic device which has short start-up time after supply of power is stopped, is highly integrated, and operates with low power. In a programmable logic device including an input/output block, a plurality of logic blocks each including a logic element, and a wiring connecting the plurality of logic blocks, the logic element has a configuration memory for holding configuration data and a look-up table including a selection circuit. The configuration memory includes a plurality of memory elements each of which includes a transistor whose channel region is in an oxide semiconductor film and an arithmetic circuit provided between the transistor and the selection circuit. Configuration data is selectively changed and output by the selection circuit in accordance with an input signal.

44. 发明申请

US20130130450A1 LOW LEAKAGE CAPACITOR FOR ANALOG FLOATING-GATE INTEGRATED CIRCUITS 有权
标题翻译：用于模拟浮动门集成电路的低泄漏电容
公开(公告)号：US20130130450A1
公开(公告)日：2013-05-23
申请号：US13718485
申请日：2012-12-18
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Imran Mahmood Khan , Allan T. Mitchell , Kaiping Liu
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , G11C27/005 , G11C2216/10 , H01L27/1156 , H01L27/11803 , H01L28/40 , H01L28/60 , H01L29/7883 , H01L29/8616
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

45. 发明申请

US20130087880A1 MEMS DEVICE AND METHOD OF MANUFACTURE 有权
标题翻译： MEMS器件及其制造方法
公开(公告)号：US20130087880A1
公开(公告)日：2013-04-11
申请号：US13646864
申请日：2012-10-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： James N. Hall , Lance W. Barron , Cuiling Gong
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L27/118 , G11C23/00 , H01L21/77 , H01L27/11803
摘要： A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels, and two body bias elements under the gate, one on each side of the torsion hinge, so that applying a threshold bias between one body bias element and the gate will pivot the gate so that one channel connects the respective source and drain landing pad, and vice versa. An integrated circuit with MEMS logic devices on the dielectric layer, with the source and drain landing pads connected to metal interconnects of the integrated circuit. A process of forming the MEM switch.
摘要翻译： MEMS逻辑器件包括在扭转铰链上枢转的玛瑙，门上的两个导电通道，扭转铰链的每一侧上的一个，通道下的源极和漏极着陆焊盘以及栅极下方的两个体偏置元件扭转铰链的一侧，使得在一个主体偏置元件和门之间施加阈值偏压将使浇口枢转，使得一个通道连接相应的源极和漏极着陆焊盘，反之亦然。在介质层上具有MEMS逻辑器件的集成电路，源极和漏极着陆焊盘连接到集成电路的金属互连。形成MEM开关的过程。

46. 发明申请

US20130064005A1 TUNNEL TRANSISTOR, LOGICAL GATE COMPRISING THE TRANSISTOR, STATIC RANDOM-ACCESS MEMORY USING THE LOGICAL GATE AND METHOD FOR MAKING SUCH A TUNNEL TRANSISTOR 有权
标题翻译：隧道晶体管，包含晶体管的逻辑门，使用逻辑门的静态随机存取存储器和制造这样的隧道晶体管的方法
公开(公告)号：US20130064005A1
公开(公告)日：2013-03-14
申请号：US13587733
申请日：2012-08-16
申请人： Marc Heyns , Cedric Huyghebaert , Anne S. Verhulst , Daniele Leonelli , Rita Rooyackers , Wim Dehaene
发明人： Marc Heyns , Cedric Huyghebaert , Anne S. Verhulst , Daniele Leonelli , Rita Rooyackers , Wim Dehaene
IPC分类号： H03K19/094 , H01L21/336 , G11C11/40 , H01L29/78
CPC分类号： H01L29/7391 , B82Y10/00 , H01L27/11 , H01L27/11803 , H01L29/0657 , H01L29/66977 , H01L29/7831 , H01L29/78648 , H01L29/78684
摘要： A tunnel transistor is provided comprising a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.
摘要翻译：提供隧道晶体管，其包括漏极，源极和至少第一栅极，用于控制漏极和源极之间的电流，其中分别地第一和第二栅极电介质材料的第一侧基本上沿着基本上接触并基本上接触第一和第二半导体部件。

47. 发明授权

US08324607B2 Mirrored-gate cell for non-volatile memory 有权
标题翻译：用于非易失性存储器的镜像门单元
公开(公告)号：US08324607B2
公开(公告)日：2012-12-04
申请号：US13280392
申请日：2011-10-25
申请人： Roger Glenn Rolbiecki , Andrew Carter , Yong Lu
发明人： Roger Glenn Rolbiecki , Andrew Carter , Yong Lu
IPC分类号： H01L47/00
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11803 , H01L27/228 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233
摘要： A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.
摘要翻译：一种存储器，包括至少一个可操作地连接到位线，源极线和字线的存储单元。存储单元包括具有第一源极触点，第二源极触点和第一源极触点和第二源极触点之间的位接触的基板，电连接第一源极触点和位触点的第一晶体管栅极和第二晶体管栅极电连接位触点和第二源触点。字线将第一晶体管栅极电连接到第二晶体管栅极。

48. 发明申请

US20120280331A1 Adaptive Fin Design for FinFETs 有权
标题翻译： FinFET的自适应鳍设计
公开(公告)号：US20120280331A1
公开(公告)日：2012-11-08
申请号：US13101890
申请日：2011-05-05
申请人： Tsong-Hua Ou , Shu-Min Chen , Pin-Dai Sue , Li-Chun Tien , Ru-Gun Liu
发明人： Tsong-Hua Ou , Shu-Min Chen , Pin-Dai Sue , Li-Chun Tien , Ru-Gun Liu
IPC分类号： H01L29/772 , H01L21/283 , H01L21/306
CPC分类号： H01L27/0886 , G06F17/5068 , H01L21/823431 , H01L27/0924 , H01L27/11803
摘要： A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.
摘要翻译：设计标准单元的方法包括确定标准单元中的半导体鳍片的最小鳍间距，其中半导体鳍片是FinFET的部分; 以及确定所述标准单元上的底部金属层中的金属线的最小金属间距，其中所述最小金属间距大于所述最小鳍间距。将标准单元放置在集成电路中并在半导体晶片上实现。

49. 发明授权

US08278689B1 Memory and interconnect design in fine pitch 有权
标题翻译：存储器和互连设计在细微间距
公开(公告)号：US08278689B1
公开(公告)日：2012-10-02
申请号：US13236312
申请日：2011-09-19
申请人： Qiang Tang , Min She , Ken Liao
发明人： Qiang Tang , Min She , Ken Liao
IPC分类号： H01L23/52
CPC分类号： H01L23/522 , H01L27/105 , H01L27/10882 , H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： A memory array including a diffusion layer, a poly layer, a metal one layer, a metal two layer, and a contact. The diffusion layer comprises diffusion lines extending in a first direction. The poly layer comprises poly lines extending in the first direction and being arranged on top of and insulated from the diffusion layer. The metal one layer comprises metal one lines extending in the first direction and being arranged on top of and insulated from the poly layer. The metal two layer comprises a metal two line extending in the first direction and being arranged on top of and insulated from the metal one layer. The contact extends through the poly layer, and connects a metal one line to a diffusion line. A poly line further extends in a second direction to bend around the contact such that a predetermined distance separates the poly lines from the contact.
摘要翻译：包括扩散层，多层，金属一层，金属二层和接触的存储器阵列。扩散层包括沿第一方向延伸的扩散线。多层包括在第一方向上延伸并且布置在扩散层的顶部并且与扩散层绝缘的多条线。金属一层包括在第一方向上延伸并且布置在多层之上并与多层绝缘的金属线。金属二层包括在第一方向上延伸并且布置在金属一层的顶部并与其绝缘的金属两条线。触点延伸穿过多层，并将金属线连接到扩散线。多线在第二方向上进一步延伸以围绕接触弯曲，使得预定距离将多线与接触分开。

50. 发明授权

US08153499B2 Method for fabrication of a semiconductor device and structure 有权
标题翻译：半导体器件和结构的制造方法
公开(公告)号：US08153499B2
公开(公告)日：2012-04-10
申请号：US13246391
申请日：2011-09-27
申请人： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong
发明人： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/76
CPC分类号： G11C17/14 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L23/36 , H01L23/481 , H01L23/5252 , H01L23/544 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L27/0207 , H01L27/0688 , H01L27/0694 , H01L27/092 , H01L27/105 , H01L27/10873 , H01L27/10876 , H01L27/10897 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/112 , H01L27/11206 , H01L27/11803 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/16145 , H01L2224/32145 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01066 , H01L2924/01322 , H01L2924/10253 , H01L2924/12032 , H01L2924/12036 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H03K17/687 , H03K19/0948 , H03K19/17704 , H03K19/17756 , H03K19/17764 , H03K19/17796 , H01L2924/00 , H01L2224/80001 , H01L2224/05599 , H01L2924/00012
摘要： A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks and at least one of the second alignment marks.
摘要翻译：一种制造半导体晶片的方法，所述方法包括：提供包括半导体衬底，金属层和第一对准标记的基底晶片; 在所述金属层的顶部上转移单晶层，其中所述单晶层包括第二对准标记; 以及使用所述第一对准标记和所述第二对准标记中的至少一个来执行光刻。

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