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1. 发明申请

US20120280331A1 Adaptive Fin Design for FinFETs 有权
标题翻译： FinFET的自适应鳍设计
公开(公告)号：US20120280331A1
公开(公告)日：2012-11-08
申请号：US13101890
申请日：2011-05-05
申请人： Tsong-Hua Ou , Shu-Min Chen , Pin-Dai Sue , Li-Chun Tien , Ru-Gun Liu
发明人： Tsong-Hua Ou , Shu-Min Chen , Pin-Dai Sue , Li-Chun Tien , Ru-Gun Liu
IPC分类号： H01L29/772 , H01L21/283 , H01L21/306
CPC分类号： H01L27/0886 , G06F17/5068 , H01L21/823431 , H01L27/0924 , H01L27/11803
摘要： A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.
摘要翻译：设计标准单元的方法包括确定标准单元中的半导体鳍片的最小鳍间距，其中半导体鳍片是FinFET的部分; 以及确定所述标准单元上的底部金属层中的金属线的最小金属间距，其中所述最小金属间距大于所述最小鳍间距。将标准单元放置在集成电路中并在半导体晶片上实现。

2. 发明授权

US08728892B2 Adaptive fin design for FinFETs 有权
标题翻译： FinFET的自适应散热片设计
公开(公告)号：US08728892B2
公开(公告)日：2014-05-20
申请号：US13101890
申请日：2011-05-05
申请人： Tsong-Hua Ou , Shu-Min Chen , Pin-Dai Sue , Li-Chun Tien , Ru-Gun Liu
发明人： Tsong-Hua Ou , Shu-Min Chen , Pin-Dai Sue , Li-Chun Tien , Ru-Gun Liu
IPC分类号： H01L21/336
CPC分类号： H01L27/0886 , G06F17/5068 , H01L21/823431 , H01L27/0924 , H01L27/11803
摘要： A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.
摘要翻译：设计标准单元的方法包括确定标准单元中的半导体鳍片的最小鳍间距，其中半导体鳍片是FinFET的部分; 以及确定所述标准单元上的底部金属层中的金属线的最小金属间距，其中所述最小金属间距大于所述最小鳍间距。将标准单元放置在集成电路中并在半导体晶片上实现。

3. 发明申请

US20120280287A1 Integrated Circuit Layouts with Power Rails under Bottom Metal Layer 有权
标题翻译：集成电路布局与底层金属层下的电源轨
公开(公告)号：US20120280287A1
公开(公告)日：2012-11-08
申请号：US13098925
申请日：2011-05-02
申请人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
发明人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
IPC分类号： H01L29/76 , H01L23/48
CPC分类号： H01L27/11807 , H01L23/5286 , H01L27/0207 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.
摘要翻译：电路包括半导体衬底; 半导体衬底上的底部金属层，其中在半导体衬底和底部金属层之间没有附加的金属层; 以及在底部金属层下方包括插头级电源轨的电池。

4. 发明授权

US08507957B2 Integrated circuit layouts with power rails under bottom metal layer 有权
标题翻译：集成电路布局与底部金属层下的电源轨
公开(公告)号：US08507957B2
公开(公告)日：2013-08-13
申请号：US13098925
申请日：2011-05-02
申请人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
发明人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
IPC分类号： H01L23/48 , H01L21/768 , H01L29/41
CPC分类号： H01L27/11807 , H01L23/5286 , H01L27/0207 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.
摘要翻译：电路包括半导体衬底; 半导体衬底上的底部金属层，其中在半导体衬底和底部金属层之间没有附加的金属层; 以及在底部金属层下方包括插头级电源轨的电池。

5. 发明申请

US20120131528A1 METHOD AND APPARATUS FOR ACHIEVING MULTIPLE PATTERNING TECHNOLOGY COMPLIANT DESIGN LAYOUT 有权
标题翻译：实现多种图案技术的方法和装置合规设计布局
公开(公告)号：US20120131528A1
公开(公告)日：2012-05-24
申请号：US12953661
申请日：2010-11-24
申请人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
发明人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G03F7/70433 , G03F7/70466
摘要： A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.
摘要翻译：提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有彩色图案布局的特点。每个面具都包含单一颜色的特征。

6. 发明授权

US08365102B2 Method for checking and fixing double-patterning layout 有权
标题翻译：双图案布局的检查和固定方法
公开(公告)号：US08365102B2
公开(公告)日：2013-01-29
申请号：US12788789
申请日：2010-05-27
申请人： Dio Wang , Ken-Hsien Hsieh , Huang-Yu Chen , Li-Chun Tien , Ru-Gun Liu , Lee-Chung Lu
发明人： Dio Wang , Ken-Hsien Hsieh , Huang-Yu Chen , Li-Chun Tien , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/00 , G06F17/5077 , G06F2217/12 , G21K5/00
摘要： A method and system checks a double patterning layout and outputs a representation of G0-rule violations and critical G0-spaces. The method includes receiving layout data having patterns, determining whether each distance between adjacent pattern elements is a G0-space, find all G0-space forming a G0-rule violation, finding all G0-space that are critical G0-spaces, and outputting a representation of G0-rule violations and critical G0-spaces to an output device. By resolving G0-rule violations and critical G0-spaces, a design checker can effectively generate a double patterning technology (DPT) compliant layout.
摘要翻译：一种方法和系统检查双重图案化布局，并输出G0规则违规和关键G0空格的表示。该方法包括接收具有图案的布局数据，确定相邻图案元素之间的每个距离是否是G0空间，找到形成G0规则违例的所有G0空间，找到作为关键G0空间的所有G0空间，并输出将G0规则违规和关键G0空格表示为输出设备。通过解决G0规则违规和关键G0空间，设计检查器可以有效地生成符合双图案技术（DPT）的布局。

7. 发明授权

US08418111B2 Method and apparatus for achieving multiple patterning technology compliant design layout 有权
标题翻译：用于实现多种图案化技术兼容的设计布局的方法和装置
公开(公告)号：US08418111B2
公开(公告)日：2013-04-09
申请号：US12953661
申请日：2010-11-24
申请人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
发明人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G03F7/70433 , G03F7/70466
摘要： A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.
摘要翻译：提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有彩色图案布局的特点。每个面具都包含单一颜色的特征。

8. 发明授权

US07808051B2 Standard cell without OD space effect in Y-direction 有权
标题翻译：标准电池在Y方向没有OD空间效应
公开(公告)号：US07808051B2
公开(公告)日：2010-10-05
申请号：US12345372
申请日：2008-12-29
申请人： Yung-Chin Hou , Lee-Chung Lu , Ta-Pen Guo , Li-Chun Tien , Ping Chung Li , Chun-Hui Tai , Shu-Min Chen
发明人： Yung-Chin Hou , Lee-Chung Lu , Ta-Pen Guo , Li-Chun Tien , Ping Chung Li , Chun-Hui Tai , Shu-Min Chen
IPC分类号： H01L29/76
CPC分类号： H01L27/0207 , H01L27/11807
摘要： An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.
摘要翻译：集成电路结构包括半导体衬底; 半导体衬底中的第一有源区; 以及在所述半导体衬底中并且具有与所述第一有源区相反的导电类型的第二有源区。栅电极条在第一和第二有源区之上，分别形成具有第一有源区和第二有源区的第一MOS器件和第二MOS器件。第一间隔棒位于半导体衬底中并与第一有源区连接。第一间隔条的至少一部分与第一有源区的一部分相邻并间隔开。第二间隔杆位于半导体衬底中并连接到第二有源区。第二间隔杆的至少一部分与第二有源区的一部分相邻并间隔开。

9. 发明授权

US09312260B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US09312260B2
公开(公告)日：2016-04-12
申请号：US13086186
申请日：2011-04-13
申请人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
发明人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
IPC分类号： H01L29/76 , H01L27/092 , H01L21/8238 , H01L23/485 , H01L27/02 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L29/0649 , H01L29/4238 , H01L29/495 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域分离。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属结构与第一源区电耦合。第二金属结构与第二漏区电耦合。第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

10. 发明申请

US20100078725A1 Standard Cell without OD Space Effect in Y-Direction 有权
标题翻译：标准电池在Y方向没有OD空间效应
公开(公告)号：US20100078725A1
公开(公告)日：2010-04-01
申请号：US12345372
申请日：2008-12-29
申请人： Yung-Chin Hou , Lee-Chung Lu , Ta-Pen Guo , Li-Chun Tien , Ping Chung Li , Chun-Hui Tai , Shu-Min Chen
发明人： Yung-Chin Hou , Lee-Chung Lu , Ta-Pen Guo , Li-Chun Tien , Ping Chung Li , Chun-Hui Tai , Shu-Min Chen
IPC分类号： H01L27/088 , H01L29/06
CPC分类号： H01L27/0207 , H01L27/11807
摘要： An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.
摘要翻译：集成电路结构包括半导体衬底; 半导体衬底中的第一有源区; 以及在所述半导体衬底中并且具有与所述第一有源区相反的导电类型的第二有源区。栅电极条在第一和第二有源区之上，分别形成具有第一有源区和第二有源区的第一MOS器件和第二MOS器件。第一间隔棒位于半导体衬底中并与第一有源区连接。第一间隔条的至少一部分与第一有源区的一部分相邻并间隔开。第二间隔杆位于半导体衬底中并连接到第二有源区。第二间隔杆的至少一部分与第二有源区的一部分相邻并间隔开。

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