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41. 发明授权

US06438622B1 Multiprocessor system including a docking system 有权
标题翻译：多处理器系统包括对接系统
公开(公告)号：US06438622B1
公开(公告)日：2002-08-20
申请号：US09193269
申请日：1998-11-17
申请人： Siamack Haghighi , Neil W. Songer
发明人： Siamack Haghighi , Neil W. Songer
IPC分类号： G06F1300
CPC分类号： G06F1/1632 , G06F15/7864
摘要： A system includes a docking base unit having a first processor and a portable computing device that is dockable to the docking base unit that includes a second processor. A module identifies the number of processors in the system once the portable computing device is docked to the docking base unit and configures the system as a multiprocessor system if more than one processor is identified.
摘要翻译：系统包括具有第一处理器和便携式计算设备的对接基座单元，该便携式计算设备可对接到包括第二处理器的对接基座单元。一旦便携式计算设备对接到对接基座单元，则模块识别系统中的处理器数量，并且如果识别出多于一个的处理器，则将系统配置为多处理器系统。

42. 发明授权

US06256722B1 Data processing system including a shared memory resource circuit 有权
标题翻译：数据处理系统包括共享存储器资源电路
公开(公告)号：US06256722B1
公开(公告)日：2001-07-03
申请号：US09459432
申请日：1999-12-13
申请人： John D. Acton , Michael D. Derbish , Gavin G. Gibson , Jack M. Hardy, Jr. , Hugh M. Humphreys , Steven P. Kent , Steven E. Schelong , Ricardo Yong , William B. DeRolf
发明人： John D. Acton , Michael D. Derbish , Gavin G. Gibson , Jack M. Hardy, Jr. , Hugh M. Humphreys , Steven P. Kent , Steven E. Schelong , Ricardo Yong , William B. DeRolf
IPC分类号： G06F1500
CPC分类号： G06F15/17381 , G06F15/7864 , H04L12/42
摘要： A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sense data, a serializer for serializing queued data, a transmitter for transmitting serialized data onto the serial bus to a next successive processing node, a receiver for receiving serialized data from a preceding processing node, and a deserializer for transforming received serialized data into a parallel format.
摘要翻译：数据处理系统包括多个节点和串行数据总线，这些节点将节点串联在闭环中，用于传递地址和数据信息。至少一个处理节点包括处理器，印刷电路板和被划分成多个部分的存储器，该存储器包括位于印刷电路板上的用于直接共享存储器的第一部分和用于阻止可共享存储器的第二部分。本地总线连接处理器，阻止共享存储器和印刷电路板，用于将数据从处理器并行传输到印刷电路板上的直接共享存储器，并将数据从块可共享存储器传送到印刷电路板。印刷电路板包括用于感测何时将数据传送到直接共享的存储器中的传感器，用于排列感测数据的排队装置，用于串行排队的数据的串行器，用于将串行化数据发送到串行总线上的下一个连续处理节点，用于从前一处理节点接收串行化数据的接收器，以及用于将接收到的串行化数据变换成并行格式的解串器。

43. 发明申请

US20010002449A1 PROCESSOR UNIT FOR A DATA-PROCESSING-AIDED ELECTRONIC CONTROL SYSTEM IN A MOTOR VEHICLE 失效
标题翻译：电动车辆中数据处理辅助电子控制系统的处理器单元
公开(公告)号：US20010002449A1
公开(公告)日：2001-05-31
申请号：US09192215
申请日：1998-11-16
申请人： DAIMLER-BENZ AKTIENGESELLSCHAFT AND INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： JOACHIM EISENMANN , STEFAN GLEISSNER , PHILIPP LANCHES , MARKUS MROSSKO , HANS-JUERGEN AMINGER , WOLFGANG EIBACH , VOLKMAR GOETZE , MATTHIAS GRUETZNER , NORBERT HAGSPIEL , MATTHIAS KOEHN , MARTIN NEUMANN , REINER RIEKE , DIETER STAIGER
IPC分类号： G06F013/12
CPC分类号： G06F15/7864 , G06F9/3877
摘要： A processor unit for a data-processing-aided electronic control system in a motor vehicle, in which the processor unit operates in real-time and contains within its functional structure a scalable computing unit and a vehicle interface unit, as well as (preferably) a communication coprocessor as separate structural components.
摘要翻译：一种用于机动车辆中的数据处理辅助电子控制系统的处理器单元，其中处理器单元实时操作并且在其功能结构内包含可扩展计算单元和车辆接口单元，以及（优选地）通信协处理器作为单独的结构组件。

44. 发明授权

US6006327A Option setting device and method for providing various settings through software means to a computer motherboard 有权
标题翻译：用于通过软件提供各种设置到计算机主板的选项设置装置和方法
公开(公告)号：US6006327A
公开(公告)日：1999-12-21
申请号：US131569
申请日：1998-08-10
申请人： Wen-Ching Chang , Yen-Liang Chen , Minjay Su
发明人： Wen-Ching Chang , Yen-Liang Chen , Minjay Su
IPC分类号： G06F15/78 , G06F15/00
CPC分类号： G06F15/7864
摘要： An option setting device and method is provided for use on a computer mother-board for providing various user-defined settings to the motherboard. The motherboard includes a CPU, a chip set coupled to the CPU, a clock generator coupled to the chip set, a delay circuit coupled to the chip set, a first latching circuit coupled to the chip set, and a reset circuit coupled to the delay circuit. After the motherboard is power on, the CPU transfers a first setting via the chip set to the first latching circuit so as to allow the first setting to be latched in the first latching circuit, and meanwhile triggers the delay circuit to start counting time. The delay circuit outputs a trigger signal to the reset circuit after a preset time, causing the reset circuit to restart the motherboard. After the motherboard is restarted, the chip set fetches the first setting from the first latching circuit so as to be set accordingly. In the case of the motherboard further having a voltage regulator, the option setting device and method further utilizes a second latching circuit for latching a second setting from the CPU and then transferring the latched setting to the voltage regulator to cause the voltage regulator to output a voltage accordingly.
摘要翻译：提供了一种在计算机母板上用于向主板提供各种用户定义的设置的选项设置装置和方法。主板包括CPU，耦合到CPU的芯片组，耦合到芯片组的时钟发生器，耦合到芯片组的延迟电路，耦合到芯片组的第一锁存电路以及耦合到延迟的复位电路电路。在主板上电之后，CPU通过芯片组将第一设置传送到第一锁存电路，以便允许第一设置被锁存在第一锁存电路中，同时触发延迟电路开始计数时间。延迟电路在预设时间后向复位电路输出触发信号，导致复位电路重启主板。在主板重新启动之后，芯片组从第一个锁存电路取出第一个设置，以便相应地进行设置。在主板还具有电压调节器的情况下，选项设置装置和方法还利用第二锁存电路来锁存来自CPU的第二设置，然后将锁存的设置传送到电压调节器，以使电压调节器输出电压相应。

45. 发明授权

US5898892A Computer system with a data cache for providing real-time multimedia data to a multimedia engine 失效
标题翻译：具有用于向多媒体引擎提供实时多媒体数据的数据高速缓存的计算机系统
公开(公告)号：US5898892A
公开(公告)日：1999-04-27
申请号：US650941
申请日：1996-05-17
申请人： Dale E. Gulick , Andy Lambrecht , Mike Webb , Larry Hewitt , Brian Barnes
发明人： Dale E. Gulick , Andy Lambrecht , Mike Webb , Larry Hewitt , Brian Barnes
IPC分类号： G06F15/78 , G06F13/12
CPC分类号： G06F15/7857 , G06F15/7846 , G06F15/7864
摘要： A computer system and method optimized for real-time multimedia applications are presented. The computer system, including a dedicated multimedia engine coupled directly to a real-time data cache, provides increased performance over current computer architectures. The multimedia engine includes at least one DSP engines which couple through at least one I/O channels to I/O ports. Obtaining multimedia commands and data from main memory and/or the real-time data cache, the multimedia engine performs a number of multimedia operations including audio and video functions. A CPU, coupled through a chip set logic or bridge logic to the main memory, generates multimedia commands and data. The CPU groups multimedia commands and data into separate command and data elements, and writes the command and data elements to a multimedia address space in main memory. The CPU also writes element structure information to the multimedia address space. The element structure information includes location information used to retrieve multimedia commands and data from main memory. The real-time data cache allows multimedia data from an external source to be stored in a location other than main memory, and allows this multimedia data to be shared by the CPU and the multimedia engine. The real-time data cache may also store multimedia commands and data for use by the multimedia engine.
摘要翻译：介绍了一种针对实时多媒体应用优化的计算机系统和方法。计算机系统，包括直接耦合到实时数据缓存的专用多媒体引擎，提供了超过当前计算机体系结构的性能。多媒体引擎包括至少一个通过至少一个I / O通道耦合到I / O端口的DSP引擎。从主存储器和/或实时数据高速缓存获取多媒体命令和数据，多媒体引擎执行包括音频和视频功能的多种多媒体操作。通过芯片组逻辑或桥接逻辑耦合到主存储器的CPU产生多媒体命令和数据。 CPU将多媒体命令和数据分组到单独的命令和数据元素中，并将命令和数据元素写入主存储器中的多媒体地址空间。 CPU还将元素结构信息写入多媒体地址空间。元素结构信息包括用于从主存储器检索多媒体命令和数据的位置信息。实时数据高速缓存允许来自外部源的多媒体数据被存储在主存储器以外的位置，并允许该多媒体数据由CPU和多媒体引擎共享。实时数据高速缓存还可以存储由多媒体引擎使用的多媒体命令和数据。

46. 发明授权

US5832248A Semiconductor integrated circuit having CPU and multiplier 失效
标题翻译：具有CPU和乘法器的半导体集成电路
公开(公告)号：US5832248A
公开(公告)日：1998-11-03
申请号：US555262
申请日：1995-11-08
申请人： Kazumasa Kishi , Shigeki Masumura , Hideo Nakamura , Kouki Noguchi , Shumpei Kawasaki , Yasushi Akao
发明人： Kazumasa Kishi , Shigeki Masumura , Hideo Nakamura , Kouki Noguchi , Shumpei Kawasaki , Yasushi Akao
IPC分类号： G06F7/52 , G06F7/506 , G06F7/523 , G06F9/302 , G06F9/32 , G06F9/38 , G06F15/78 , G06F12/00
CPC分类号： G06F9/3001 , G06F15/7864 , G06F9/325 , G06F9/3885
摘要： A logic LSI chip includes a CPU, a bus, a memory, and a multiplier. In addition, the logic LSI chip includes a command signal line for transferring, from the CPU to the multiplier, a command regarding a multiplication instruction relating to data read out, while the data is being read out from the memory, so that the multiplier can fetch the data directly from the bus. While the CPU is reading data from the memory, therefore, a command of a multiplication instruction relating to data read out is transferred from the CPU to the multiplier. A bus cycle control circuit receives a state signal from the multiplier when the multiplier is executing a repetitional operation and the bus cycle control circuit responds to the state signal by signalling the CPU to delay issuance of a succeeding command to the multiplier.
摘要翻译：逻辑LSI芯片包括CPU，总线，存储器和乘法器。此外，逻辑LSI芯片包括用于在从存储器读出数据的同时从CPU向乘法器传送关于与读出的数据相关的乘法指令的命令的命令信号线，使得乘法器从总线直接获取数据。因此，当CPU从存储器读取数据时，与读出的数据相关的乘法指令的命令从CPU传送到乘法器。当乘法器执行重复操作时，总线周期控制电路接收来自乘法器的状态信号，并且总线周期控制电路通过发信号通知CPU来延迟向乘法器发出后续命令来响应状态信号。

47. 发明授权

US4460972A Single chip microcomputer selectively operable in response to instructions stored on the computer chip or in response to instructions stored external to the chip 失效
标题翻译：单片微计算机响应于存储在计算机芯片上的指令或响应于芯片外部存储的指令而选择性地操作
公开(公告)号：US4460972A
公开(公告)日：1984-07-17
申请号：US288631
申请日：1981-07-30
申请人： Merle E. Homan , Guenther K. Machol , Larry M. Warren
发明人： Merle E. Homan , Guenther K. Machol , Larry M. Warren
IPC分类号： G06F15/78 , G06F13/00
CPC分类号： G06F15/7864
摘要： A microprocessor external instruction feature which provides for a single chip microprocessor with on-chip read only instruction store (ROS) that can also be operated with an off-chip instruction store. To accomplish this, the microprocessor instruction sequencing logic (instruction store, instruction register, instruction counter, and sequencing logic) is duplicated off-chip. An XI MODE input pin signal causes the microprocessor to take its instructions from the external instruction store via 12 XI input pins instead of from the on-chip ROS. A BR DECISION output pin signal from the microprocessor, which indicates that the branch conditions have been met, causes the external instruction counter to be loaded with a branch address from the external instruction register instead of being stepped by external sequencing logic. A WAIT output pin signal causes the external instruction feature logic to suspend operations while the microprocessor is in its wait state.
摘要翻译：一种微处理器外部指令功能，它为单芯片微处理器提供片上只读指令存储器（ROS），也可以使用片外指令存储器进行操作。为了实现这一点，微处理器指令排序逻辑（指令存储器，指令寄存器，指令计数器和排序逻辑）在片外复制。一个XI MODE输入引脚信号使微处理器通过12个XI输入引脚而不是片上ROS从外部指令存储器中取出指令。来自微处理器的BR DECISION输出引脚信号，表示分支条件已被满足，使得外部指令计数器从外部指令寄存器加载分支地址，而不是由外部排序逻辑进行步进。当微处理器处于等待状态时，等待输出引脚信号使外部指令特征逻辑暂停操作。

48. 发明授权

US3975714A Data processing system including an LSI chip containing a memory and its own address register 失效
标题翻译：数据处理系统包括含有存储器的LSI芯片及其自己的地址寄存器
公开(公告)号：US3975714A
公开(公告)日：1976-08-17
申请号：US535092
申请日：1974-12-20
申请人： Gerald Weber , Jurgen Sorgenfrei
发明人： Gerald Weber , Jurgen Sorgenfrei
IPC分类号： G06F12/02 , G06F12/06 , G06F15/78 , G06F13/00
CPC分类号： G06F15/7864 , G06F12/06
摘要： In a circuit arrangement composed of chips containing highly integrated MOS circuit components for a data processing device, the arrangement including a first chip containing a central arithmetic and control unit, a plurality of further chips each containing a memory, and a bus connecting the chips, each further chip is provided with its own address register for addressing the memory on that chip, and the register is capable of being set to contain any desired address word and to selectively count through a sequence of successive address words under control of counting pulses, each address word identifying a respective word location of the associated memory.
摘要翻译：在由包含用于数据处理装置的高度集成的MOS电路部件的芯片构成的电路装置中，该装置包括包含中央计算和控制单元的第一芯片，每个包含存储器的多个另外的芯片以及连接芯片的总线，每个另外的芯片都设置有自己的地址寄存器，用于寻址该芯片上的存储器，并且寄存器能够被设置为包含任何期望的地址字，并且可以在计数脉冲的控制下选择性地对连续地址字序列进行计数，识别相关存储器的相应字位置的地址字。

49. 发明授权

US3972028A Data processing system including a plurality of memory chips each provided with its own address register 失效
标题翻译：数据处理系统包括多个存储器芯片，每个存储器芯片设有自己的地址寄存器
公开(公告)号：US3972028A
公开(公告)日：1976-07-27
申请号：US535089
申请日：1974-12-20
申请人： Gerald Weber , Jurgen Sorgenfrei
发明人： Gerald Weber , Jurgen Sorgenfrei
IPC分类号： G06F9/22 , G06F9/32 , G06F9/42 , G06F12/02 , G06F12/06 , G06F15/78 , G06F13/00
CPC分类号： G06F12/06 , G06F15/7864 , G06F12/0215
摘要： In a circuit arrangement composed of a plurality of highly integrated MOS circuit chips, for use in a data processing device, one chip being an arithmetic and control unit and further chips containing memories, each further chip is also provided with an address register capable of storing a selected memory location address and an address selecting the memory of a selected memory chip for read-out and arranged to count through the successive memory location addresses and to change the memory selecting address after the count reaches the last memory location address, such counting being effected by counting pulses.
摘要翻译：在由多个高度集成的MOS电路芯片构成的电路装置中，在数据处理装置中使用的一个芯片是运算和控制单元以及包含存储器的另外的芯片，每个芯片还提供有能够存储的地址寄存器选择的存储器位置地址和选择所选择的用于读出的存储器芯片的存储器的地址，并且被布置成通过连续存储器位置地址进行计数，并且在计数到达最后存储器位置地址之后改变存储器选择地址，这样计数为通过计数脉冲来实现。

50. 发明授权

US3900722A Multi-chip calculator system having cycle and subcycle timing generators 失效
标题翻译：具有循环和小时同步发电机的多芯片计算机系统
公开(公告)号：US3900722A
公开(公告)日：1975-08-19
申请号：US39706073
申请日：1973-09-13
申请人： TEXAS INSTRUMENTS INC
发明人： COCHRAN MICHAEL J , GRANT JR CHARLES P
IPC分类号： G06F9/26 , G06F13/42 , G06F15/02 , G06F15/78 , G06F1/04
CPC分类号： G06F13/423 , G06F9/261 , G06F9/264 , G06F15/02 , G06F15/7864
摘要： An electronic protable calculator implemented in integrated circuit semiconductor technology utilizes cycle and subcycle timing generators on both the arithmetic chip and on the memory chip. One output terminal conveys both an internal operating condition of the arithmetic to other semiconductor calculator chips in the system including to the memory chip, and also conveys timing synchronization for the cycle and subcycle timing generators on the memory chip. The arithmetic chip also has means for generating a multi-bit command signal comprising a first set of bits representing internal conditions of the arithmetic chip and a second set of bits selectively representing a memory address location dependent upon bits in the first set.

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