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1. 发明授权

US3900722A Multi-chip calculator system having cycle and subcycle timing generators 失效
标题翻译：具有循环和小时同步发电机的多芯片计算机系统
公开(公告)号：US3900722A
公开(公告)日：1975-08-19
申请号：US39706073
申请日：1973-09-13
申请人： TEXAS INSTRUMENTS INC
发明人： COCHRAN MICHAEL J , GRANT JR CHARLES P
IPC分类号： G06F9/26 , G06F13/42 , G06F15/02 , G06F15/78 , G06F1/04
CPC分类号： G06F13/423 , G06F9/261 , G06F9/264 , G06F15/02 , G06F15/7864
摘要： An electronic protable calculator implemented in integrated circuit semiconductor technology utilizes cycle and subcycle timing generators on both the arithmetic chip and on the memory chip. One output terminal conveys both an internal operating condition of the arithmetic to other semiconductor calculator chips in the system including to the memory chip, and also conveys timing synchronization for the cycle and subcycle timing generators on the memory chip. The arithmetic chip also has means for generating a multi-bit command signal comprising a first set of bits representing internal conditions of the arithmetic chip and a second set of bits selectively representing a memory address location dependent upon bits in the first set.

2. 依法登记的发明

USH1970H Variable function programmed system 失效
标题翻译：变量功能编程系统
公开(公告)号：USH1970H
公开(公告)日：2001-06-05
申请号：US47354190
申请日：1990-02-01
申请人： TEXAS INSTRUMENTS INC
发明人： BOONE GARY W , COCHRAN MICHAEL J
IPC分类号： G06F3/14 , G06F15/02 , G09G3/04 , G06F15/00
CPC分类号： G09G3/04 , G06F3/1407 , G06F15/02
摘要： A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, digit and FLAG mask decoders, key input logic, a register and FLAG data storage array, a decimal and FLAG arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc.. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.
摘要翻译：可变函数计算器利用诸如编程的只读存储器的固定程序存储器阵列，其中根据计算器的期望功能存储多个程序。计算器还包括程序计数器，指令寄存器，控制解码器，跳转条件电路，时钟发生器，定时发生器，数字和FLAG掩码解码器，键输入逻辑，寄存器和FLAG数据存储阵列，小数和FLAG 算术逻辑单元，输出解码器和扫描键盘和显示输出的数字扫描器。除了提供基本的桌面计算器功能之外，只读存储器可以被编程，使得系统提供测量功能，算术教学功能，控制功能等。本发明的优选实施例能够被制造为单片集成半导体利用当代金属绝缘体半导体技术的系统。

3. 发明授权

US3919536A Precharged digital adder and carry circuit 失效
标题翻译：预充电数字加法器和进位电路
公开(公告)号：US3919536A
公开(公告)日：1975-11-11
申请号：US39704873
申请日：1973-09-13
申请人： TEXAS INSTRUMENTS INC
发明人： COCHRAN MICHAEL J , GRANT JR CHARLES P
IPC分类号： G06F7/50 , G06F7/503
CPC分类号： G06F7/503 , G06F7/495 , G06F2207/3844 , G06F2207/3872
摘要： Disclosed is a calculator system featuring a precharged carry propagate arithmetic logic circuit. A plurality of data registers store in parallel a plurality of multi-bit data words and are coupled in parallel to the arithmetic logic circuit for executing arithmetic and logic operations thereon. The arithmetic logic circuit is responsive to instruction words for executing either an addition or a subtraction function. A carry propagate circuit is provided for precharging a carry terminal of each bit in the ALU to a reference potential along with a circuit associated with each bit for selectively discharging the carry terminal responsive to the logic level of the previous carry signal into each bit and is further responsive to the appropriate bits of the data words. An exclusive-or adder circuit has an adder terminal precharged to a reference potential during one phase of a clock signal, and further has a discharge circuit for selectively discharging the terminal in response to logic levels of the appropriate bits of the data word and responsive to the carry signal.
摘要翻译：公开了一种具有预充电进位传播算术逻辑电路的计算器系统。多个数据寄存器并行存储多个多位数据字，并且并行耦合到算术逻辑电路，用于对其执行算术和逻辑运算。算术逻辑电路响应于用于执行加法或减法函数的指令字。提供进位传播电路，用于将ALU中的每个位的进位端子预先充电到参考电位以及与每个位相关联的电路，以便响应于先前进位信号的逻辑电平而选择性地将进位端子放电到每个位中，并且是进一步响应数据字的适当位。异或加法器电路具有在时钟信号的一个相位期间预充电到参考电位的加法器端子，并且还具有放电电路，用于响应于数据字的适当位的逻辑电平有选择地对端子进行放电，并响应于进位信号。

4. 发明授权

US3922538A Calculator system featuring relative program memory 失效
标题翻译：具有相对程序存储器的计算器系统
公开(公告)号：US3922538A
公开(公告)日：1975-11-25
申请号：US39690273
申请日：1973-09-13
申请人： TEXAS INSTRUMENTS INC
发明人： COCHRAN MICHAEL J , GRANT JR CHARLES P
IPC分类号： G06F9/26 , G06F9/20
CPC分类号： G06F9/264 , G06F9/261
摘要： Disclosed is a portable hand-held calculator system implemented in semiconductor LSI technology which features relative instruction memory addressing. A permanent store instruction memory is provided for storing a relatively large number of instruction words at specific addresses with each instruction word providing either a branch or an instrction command. The instruction word is a multi-bit word which, if one bit therein commands a conditional branch, has a set of digits representing a relative address number which either positively or negatively increments the old address to provide the address next in sequence. Another bit of the instruction word is a condition bit utilized in a compare with a representation of an internal operating condition of the calculator system. If a proper match is realized, a conditional branch is executed. A full adder selectively increments the previous instruction word in response to the relative address to generate the new instruction word.
摘要翻译：公开了以半导体LSI技术实现的便携式手持计算器系统，其特征在于具有相对指令存储器寻址。提供永久存储指令存储器，用于在每个指令字提供分支或指令命令时，在特定地址处存储相对大量的指令字。指令字是一个多位字，如果其中的一个位命令一个条件分支，则具有表示相对地址号的一组数字，该相对地址号可以正或负地递增旧地址以依次提供下一个地址。指令字的另一位是与计算器系统的内部操作条件的表示的比较中使用的条件位。如果实现了正确匹配，则执行条件分支。全加器有选择地增加先前的指令字以响应相对地址以产生新的指令字。

5. 发明授权

US3904862A Calculator system having a constant memory 失效
标题翻译：计算器系统具有恒定的内存
公开(公告)号：US3904862A
公开(公告)日：1975-09-09
申请号：US39718173
申请日：1973-09-13
申请人： TEXAS INSTRUMENTS INC
发明人： COCHRAN MICHAEL J , GRANT JR CHARLES P
IPC分类号： G06F15/02 , H03M11/20 , G06F9/10
CPC分类号： H03M11/20 , G06F15/02
摘要： Disclosed is a portable calculator system featuring a constant memory in addition to an instruction memory. The constant memory is preferably implemented as a virtual ground ROM which is addressed by the same signal which addresses the instruction memory for executing an unconditional branch. A keyboard storage register responsive to keyboard inputs provide memory address to the constant memory in a multi-digit command word having first and second sets of digits. The second set of digits represents the constant memory address which is executed only if the first set of digits so command. The second set of digits also represent a chip select signal for enabling only the specific memory on a specific memory chip if a multi-chip system is utilized.

6. 发明授权

US3919532A Calculator system having an exchange data memory register 失效
标题翻译：计算器系统具有交换数据存储寄存器
公开(公告)号：US3919532A
公开(公告)日：1975-11-11
申请号：US39718573
申请日：1973-09-13
申请人： TEXAS INSTRUMENTS INC
发明人： COCHRAN MICHAEL J , GRANT JR CHARLES P
IPC分类号： G06F15/02 , G06F13/00
CPC分类号： G06F15/02
摘要： Disclosed is an electronic calculator system implemented on at least one semiconductor chip having a first set of data storage memory registers for storing a first plurality of multi-digit, multi-bit data words, and further having another storage memory register coupled to the first set of storage registers for storing another multi-digit, multi-bit data word. The said another storage means has an input which is responsive only to one of the first set, under control of an instruction word provided by a permanent store memory. The system further provides an N input arithmetic means coupled to the N data storage means such that (including the said another register) there are N + 1 storage registers providing inputs to the N input adder. By providing the exchange register having inputs and outputs coupled to only one of the first set, input and output select circuitry is eliminated to effect increased packing density.
摘要翻译：公开了一种在至少一个半导体芯片上实现的电子计算器系统，该半导体芯片具有第一组数据存储存储器寄存器，用于存储第一多个多位多位数据字，并且还具有耦合到第一组的另一存储器寄存器的存储寄存器用于存储另一个多位，多位数据字。所述另一个存储装置具有在由永久存储存储器提供的指令字的控制下仅响应于第一组中的一个的输入。该系统进一步提供一个耦合到N个数据存储装置的N输入算术装置，使得（包括所述另一个寄存器）存在向N个输入加法器提供输入的N + 1个存储寄存器。通过提供具有仅耦合到第一组中的一个的输入和输出的交换寄存器，消除了输入和输出选择电路以实现增加的堆积密度。

7. 发明授权

US3902054A Calculator system having keyboard with double entry protection and serialized encoding 失效
标题翻译：具有双重进入保护和串行编码的键盘的计算机系统
公开(公告)号：US3902054A
公开(公告)日：1975-08-26
申请号：US39695973
申请日：1973-09-13
申请人： TEXAS INSTRUMENTS INC
发明人： COCHRAN MICHAEL J , GRANT JR CHARLES P
IPC分类号： G06F15/02 , H03M11/20 , G06F3/02
CPC分类号： H03M11/20 , G06F15/02
摘要： Disclosed is a calculator system having a keyboard providing double entry protection. The keyboard comprises an array of keys in rows and columns with the columns strobed in sequence by cycle times of the calculator system. An encoder coupled to the rows of the keys provides encoded representations of particular row actuation upon a specific key depression. Both true and complement representations are provided for preventing double entry. A serializer is responsive to the encoder for serializing the row line representation and the particular cycle time to define the particular key actuated and to define a new instruction memory address. The serialized representation is stored in a memory register in synchronization with subcycle times for eventually addressing an instruction memory.
摘要翻译：公开了一种除了指令存储器之外还具有恒定存储器的便携式计算器系统。恒定存储器优选地被实现为由寻址用于执行无条件分支的指令存储器的相同信号寻址的虚拟接地ROM。响应于键盘输入的键盘存储寄存器以具有第一和第二组数字的多位指令字向常数存储器提供存储器地址。第二组数字表示只有当第一组数字如此命令时才执行的常量存储器地址。如果使用多芯片系统，则第二组数字还表示用于仅使特定存储器芯片上的特定存储器实现的芯片选择信号。

8. 发明授权

US3924110A Calculator system featuring a subroutine register 失效
标题翻译：具有子程序寄存器的计算器系统
公开(公告)号：US3924110A
公开(公告)日：1975-12-02
申请号：US39705673
申请日：1973-09-13
申请人： TEXAS INSTRUMENTS INC
发明人： COCHRAN MICHAEL J , GRANT JR CHARLES P
IPC分类号： G06F9/445 , G06F15/78 , G06F9/20
CPC分类号： G06F9/445 , G06F15/7864
摘要： Disclosed is a portable electronic calculator system implemented in LSI semiconductor technology which features subroutine storage. The subroutine storage is combined with keyboard and flag storage and is preferably implemented as a sequentially addressed memory. The system includes a permanent store memory for storing instruction words, which is addressable by the keyboard storage. After addressing the memory according to a location specified in the keyboard storage, an exchange is executed between the keyboard storage and subroutine. Subsequently, another exchange is executed effecting return of the operating program to the location in the memory previously specified. The subroutine register is under control of the instruction memory, and functions only to exchange its contents with that of the keyboard storage.
摘要翻译：公开了以LSI半导体技术实现的便携式电子计算器系统，其具有子程序存储。子程序存储器与键盘和标志存储器组合，并且优选地被实现为顺序寻址的存储器。该系统包括用于存储可由键盘存储器寻址的指令字的永久存储存储器。在根据键盘存储器中指定的位置寻址存储器之后，在键盘存储和子程序之间执行交换。随后，执行另一个交换，使操作程序返回到先前指定的存储器中的位置。子程序寄存器在指令存储器的控制下，仅用于将其内容与键盘存储器的内容进行交换。

9. 发明授权

US3922526A Driver means for lsi calculator to reduce power consumption 失效
标题翻译：驱动程序意味着lsi计算器可以降低功耗
公开(公告)号：US3922526A
公开(公告)日：1975-11-25
申请号：US32900873
申请日：1973-02-02
申请人： TEXAS INSTRUMENTS INC
发明人： COCHRAN MICHAEL J
IPC分类号： G06F1/08 , G06F1/32 , G06F3/023 , G06F15/02 , H03M11/20 , G06F1/04
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , G06F1/3228 , G06F15/02 , Y02D10/126
摘要： An MOS integrated circuit electronic calculator is clocked by a sequential tri-frequency signal generator actuable in response to the keyboard signals. The clock generator supplies a first relatively high frequency signal during the relatively short period when the calculator is actually in the calculating mode, a second intermediate frequency for a selected time interval after the calculator has completed actual calculating and is displaying the result, and a third low frequency signal after the selected time interval during which time the calculator is in a quiescent state, neither calculating nor displaying the result but merely internally retaining the previous information. The generator also supplies a strobed VGG signal to the calculator chip in response to a static VGG signal generated by a regulated power supply. Both the power supply and the tri-frequency generator are preferably formed on a single bipolar integrated circuit chip.
摘要翻译： MOS集成电路电子计算器由响应于键盘信号可启动的顺序三频信号发生器计时。时钟发生器在计算器实际处于计算模式的相对短的时间段期间提供第一相对较高频率的信号，在计算器完成实际计算之后的所选择的时间间隔的第二中间频率，并且显示结果在选择的时间间隔之后，计算器处于静止状态的低频信号，既不计算也不显示结果，仅内部保留先前的信息。发生器还响应于由稳压电源产生的静态VGG信号，向计算器芯片提供选通的VGG信号。电源和三频发生器都优选地形成在单个双极集成电路芯片上。

10. 发明授权

US3916169A Calculator system having a precharged virtual ground memory 失效
标题翻译：计算器系统具有预充电的虚拟接地存储器
公开(公告)号：US3916169A
公开(公告)日：1975-10-28
申请号：US39690173
申请日：1973-09-13
申请人： TEXAS INSTRUMENTS INC
发明人： COCHRAN MICHAEL J , GRANT JR CHARLES P
IPC分类号： G11C17/12 , G06F15/02 , G11C17/00
CPC分类号： G11C17/126
摘要： Disclosed is a calculator featuring a virtual ground permanent store instruction memory for storing and providing instruction words. The memory cells are arrayed in rows and columns which are respectively responsive to row and column address circuits. Each bit of the instruction word is outputted on a single output line, and a pair of output lines have only one ground line selectively coupling each to circuit ground. The row and column lines are precharged by decoupling the ground lines from circuit ground and precharging the respective output lines, with the column address circuitry coupling each column line to the respective output line for precharging all columns.
摘要翻译：公开了一种具有虚拟地面永久存储指令存储器的计算器，用于存储和提供指令字。存储单元以行和列排列，它们分别响应于行和列地址电路。指令字的每一位都在一条输出线上输出，一对输出线只有一条接地线选择性地耦合到电路地。行和列线通过将接地线与电路接地断开并对各个输出线进行预充电来预充电，列地址电路将每个列线耦合到相应的输出线，以预充电所有列。

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