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41. 发明授权

US09600322B1 Leveraging multiprocessor fabric link aggregation 有权
公开(公告)号：US09600322B1
公开(公告)日：2017-03-21
申请号：US14936906
申请日：2015-11-10
申请人： International Business Machines Corporation
发明人： Hariharasubramanian Ramasubramanian , Jinu J. Thomas , Venkatesh Sainath
IPC分类号： G06F3/00 , G06F9/455 , G06F13/42 , G06F13/12 , G06F3/0481 , G06F3/0484 , G06F9/54
CPC分类号： G06F9/45558 , G06F3/0481 , G06F3/0482 , G06F3/0484 , G06F9/5083 , G06F9/54 , G06F13/126 , G06F13/4234 , G06F15/17343 , G06F2009/4557 , G06F2009/45579 , G06F2009/45591 , G06F2009/45595
摘要： Data access patterns between at least three nodes within a single symmetric multiprocessing server may be monitored by at least one hypervisor. At the hypervisor, mappings for the data access patterns may be generated for the at least three nodes. Based upon the mappings, the hypervisor may determine that the data access patterns for at least two of the at least three nodes are outside of a bandwidth threshold. In response to determining that the data access patterns for at least two of the at least three nodes are outside of a bandwidth threshold, the hypervisor may formulate an asymmetric cabling plan. Based upon the asymmetric cabling plan, a recommendation to alter the multiprocessor fabric link aggregation may be displayed to a user through a graphical user interface.

42. 发明授权

US09588922B2 Techniques for inter-component communication based on a state of a chip select pin 有权
标题翻译：基于芯片选择引脚状态的组件间通信技术
公开(公告)号：US09588922B2
公开(公告)日：2017-03-07
申请号：US14668013
申请日：2015-03-25
申请人： Intel Corporation
发明人： Mikal C. Hunsaker , Su Wei Lim , Ricardo E. James
IPC分类号： G06F13/00 , G06F13/364 , G06F1/06 , G06F1/24 , G06F13/42 , G06F11/07 , G06F11/10 , G06F11/22 , G06F13/12 , G06F13/40 , G06F11/30 , G06F13/16
CPC分类号： G06F13/364 , G06F1/06 , G06F1/24 , G06F11/0727 , G06F11/0745 , G06F11/1004 , G06F11/1072 , G06F11/221 , G06F11/2289 , G06F11/3027 , G06F13/00 , G06F13/122 , G06F13/1668 , G06F13/4068 , G06F13/4221 , G06F13/423 , G06F13/4234 , G06F13/4282 , G06F13/4291 , G11C29/52
摘要： Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.
摘要翻译：具有组件间通信能力的分量设备和具有这种组件设备的系统在此被公开。在实施例中，这样的组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与其他组件的交易，以便接收通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。提供警报信号，接收状态请求和提供状态可以参考时钟信号。可以公开或要求保护其他实施例。

43. 发明申请

US20160378710A1 MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCONNECT 审中-公开
标题翻译：用于高速互连的多个交易数据流控制单元
公开(公告)号：US20160378710A1
公开(公告)日：2016-12-29
申请号：US15262415
申请日：2016-09-12
申请人： lntel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Debendra Das Sharma
IPC分类号： G06F13/42 , G06F15/78 , G06F12/0831 , G06F13/14
CPC分类号： G06F13/4282 , G06F12/0831 , G06F13/00 , G06F13/14 , G06F13/38 , G06F13/4234 , G06F13/426 , G06F15/781 , G06F2212/621 , G06F2213/0008 , G06F2213/0024 , G06F2213/0026 , H04L12/00
摘要： Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.
摘要翻译：用于通过高速互连传输包括多条交易数据的数据单元的方法，装置和系统。称为KTI（Keizer Technology Interface）的流量控制单元以支持相干存储器事务的相干多层协议实现。 KTI Flit具有一种基本格式，支持使用可配置字段来实现可用于相应事务的特定格式的KTI Flits。在一个方面，KTI Flit可以被格式化为用于支持在单个Flit中传送多个相应交易数据的多个时隙。 KTI Flit也可以配置为支持各种类型的事务，并且可以将多个KTI Flits组合成数据包，以支持数据传输，如缓存线传输。

44. 发明申请

US20160328156A1 DRAM MEMORY CHANNEL SCRAMBLING/ECC DISASSOCIATED COMMUNICATION 有权
标题翻译： DRAM存储器通道SCRAMBLING / ECC DISASSOCIATED COMMUNICATION
公开(公告)号：US20160328156A1
公开(公告)日：2016-11-10
申请号：US14967258
申请日：2015-12-11
申请人： Ian SWARBRICK , Michael BEKERMAN , Craig HANSON , Chihjen CHANG
发明人： Ian SWARBRICK , Michael BEKERMAN , Craig HANSON , Chihjen CHANG
IPC分类号： G06F3/06
CPC分类号： G06F13/4234
摘要： A protocol that enables communication between a host and an Input/Output (I/O) channel storage device, such as a Dynamic Random Access Memory (DRAM) channel Dual In-Line Memory Module (DIMM) form-factor Solid State Drive (SSD), without the need to know or reverse engineer the encoding applied by the host. The control/status data are written to the storage device by sending a protocol training sequence of known values and storing the associated command/status data in the storage device in the same encoding format as that received from the host. These stored values are used at run time to execute encoded commands received from the host and to report status data to the host in the host-recognizable manner. A memory bank-based buffered configuration stores user data also in the as-received condition to preserve the host-specific encoding. This facilitates exchange of user data between the host memory controller and the storage device over the DRAM channel.
摘要翻译：支持主机与输入/输出（I / O）通道存储设备之间的通信的协议，例如动态随机存取存储器（DRAM）通道双列直插存储器模块（DIMM）外形固态驱动器（SSD）），而不需要知道或逆向工程主机应用的编码。控制/状态数据通过发送已知值的协议训练序列并以与从主机接收的编码格式相同的编码格式将相关联的命令/状态数据存储在存储设备中而被写入存储设备。在运行时使用这些存储的值来执行从主机接收的编码命令，并以主机可识别的方式将状态数据报告给主机。基于存储体的缓冲配置也将用户数据也存储在接收状态以保存主机特定的编码。这有助于通过DRAM信道在主机存储器控制器和存储设备之间交换用户数据。

45. 发明授权

US09460110B2 File system extension system and method 有权
标题翻译：文件系统扩展系统和方法
公开(公告)号：US09460110B2
公开(公告)日：2016-10-04
申请号：US14886616
申请日：2015-10-19
申请人： Kevin Mark Klughart
发明人： Kevin Mark Klughart
IPC分类号： G06F3/00 , G06F17/30 , G06F3/06 , G06F13/42 , G06F13/38 , G06F13/00 , G06F13/28 , G06F13/37 , G06F13/40
CPC分类号： G06F17/30203 , G06F3/0607 , G06F3/0619 , G06F3/0643 , G06F3/0655 , G06F3/0658 , G06F3/0665 , G06F3/0685 , G06F3/0689 , G06F13/00 , G06F13/287 , G06F13/37 , G06F13/385 , G06F13/4068 , G06F13/4072 , G06F13/409 , G06F13/4234 , G06F13/4247 , G06F2212/262 , G06F2213/0032 , G06F2213/28 , G06F2213/3802
摘要： A file system extension (FSE) system and method that permits an on-disk-structure (ODS) incorporating spatially diverse data (SDD) to be stored on a daisy-chain of multiple SATA disk drive storage elements (DSE) that are coupled together with one or more pass-thru disk drive controllers (PTDDC) is disclosed. The PTDDC chain appears as a single logical disk drive to a host computer system (HCS) via a host bus adapter (HBA) or pass-thru input (PTI) port. The PTDDC chain may appear to the HCS as virtual disk storage (VDS) that is larger than the actual physical disk storage (PDS) contained within the DSEs. The PTDDC chain is configured to map the SDD to portions of the DSE that are actually present within the VDS and thus allow critical portions of the ODS to reside on the PTDDC chain with transparent access by an operating system running on the HCS.
摘要翻译：一种文件系统扩展（FSE）系统和方法，其允许将包含空间多样性数据（SDD）的磁盘结构（ODS）存储在耦合在一起的多个SATA磁盘驱动器存储元件（DSE）的菊花链上具有一个或多个通过磁盘驱动器控制器（PTDDC）的公开。 PTDDC链通过主机总线适配器（HBA）或通过输入（PTI）端口显示为主机计算机系统（HCS）的单个逻辑磁盘驱动器。作为虚拟磁盘存储（VDS），PTDDC链可能会显示为大于DSE中包含的实际物理磁盘存储（PDS）的HCS。 PTDDC链被配置为将SDD映射到实际存在于VDS中的DSE的部分，并且因此允许ODS的关键部分驻留在PTDDC链上，由在HCS上运行的操作系统进行透明访问。

46. 发明授权

US09444495B2 System and method of interfacing co-processors and input/output devices via a main memory system 有权
公开(公告)号：US09444495B2
公开(公告)日：2016-09-13
申请号：US14635960
申请日：2015-03-02
申请人： Diablo Technologies Inc.
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： G06F11/00 , H03M13/00 , H03M13/27 , H03M13/05 , G06F11/10 , G06F12/02 , G06F12/06 , G06F13/20 , H04L9/06 , G06F9/44 , G06F13/42
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F9/4406 , G06F11/1016 , G06F11/1076 , G06F12/0246 , G06F12/0607 , G06F13/20 , G06F13/404 , G06F13/4221 , G06F13/4234 , G06F13/4282 , G06F2212/1008 , G06F2212/1032 , G06F2212/7201 , G06F2212/7208 , H03M13/05 , H03M13/27 , H04L9/0662
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

47. 发明申请

US20160224481A1 MULTIPROCESSOR CACHE BUFFER MANAGEMENT 有权
标题翻译：多处理器缓存缓存管理
公开(公告)号：US20160224481A1
公开(公告)日：2016-08-04
申请号：US14608373
申请日：2015-01-29
申请人： International Business Machines Corporation
发明人： Ekaterina M. Ambroladze , Deanna P. Berger , Michael Fee , Arthur J. O'Neill, JR.
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42
CPC分类号： G06F13/1673 , G06F13/1652 , G06F13/4022 , G06F13/4234
摘要： In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.
摘要翻译：在用于管理由处理器共享的总线上的数据传输的方法中，从第一处理器接收对第一组数据的请求。从第二处理器接收对第二组数据的请求。将第一组数据和第二组数据的第一部分写入缓冲器。每一组数据的附加部分在接收到部分时被写入缓冲器。基于优先级方案，确定第一组数据的一部分具有比第二组数据的部分更高的总线优先级，其中优先级方案基于每个相应的数据集合的返回进程，具有缓冲区中的至少一部分数据。第一组数据的部分被授权访问总线。

48. 发明授权

US09342453B2 Memory channel that supports near memory and far memory access 有权
标题翻译：支持近内存和远程内存访问的内存通道
公开(公告)号：US09342453B2
公开(公告)日：2016-05-17
申请号：US13977603
申请日：2011-09-30
申请人： Bill Nale , Raj K. Ramanujan , Muthukumar P. Swaminathan , Tessil Thomas , Taarinya Polepeddi
发明人： Bill Nale , Raj K. Ramanujan , Muthukumar P. Swaminathan , Tessil Thomas , Taarinya Polepeddi
IPC分类号： G06F12/00 , G06F12/08 , G06F13/16 , G06F11/10 , G06F9/46 , G06F3/00
CPC分类号： G06F13/1694 , G06F9/467 , G06F11/1064 , G06F12/0238 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0868 , G06F12/0897 , G06F13/1668 , G06F13/4068 , G06F13/42 , G06F13/4234 , G06F2212/1008 , G06F2212/1016 , G06F2212/1044 , G06F2212/2024 , G06F2212/7203 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.
摘要翻译：一种包括存储器控制器电路的半导体芯片，其具有耦合到存储器通道的接口电路。存储器控制器包括在存储器通道上实现第一存储器通道协议的第一逻辑电路。第一存储器通道协议特定于第一易失性系统存储器技术。接口还包括在存储器通道上实现第二存储器通道协议的第二逻辑电路。第二存储器通道协议专用于第二非易失性系统存储器技术。第二个存储器通道协议是事务协议。

49. 发明申请

US20160132272A1 INFORMATION PROCESSING APPARATUS, COMMUNICATION METHOD AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：信息处理装置，通信方法和信息处理系统
公开(公告)号：US20160132272A1
公开(公告)日：2016-05-12
申请号：US14887382
申请日：2015-10-20
申请人： FUJITSU LIMITED
发明人： Hidetoshi Iwashita
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0644 , G06F3/0604 , G06F3/0683 , G06F3/0689 , G06F8/453 , G06F12/0802 , G06F13/385 , G06F13/387 , G06F13/4221 , G06F13/4234 , G06F2212/1016 , G06F2212/60
摘要： An information processing apparatus, among a plurality of information processing apparatuses, to which one of pieces of local data is assigned, the pieces of local data having been obtained by dividing global data shared by the plurality of information processing apparatuses, includes: a storage unit that includes a first storage area sectioned into prescribed units, and stores local data; a processor that executes a process including: detecting a plurality of continuous sections to which the target local data is to be written in a second storage area that is sectioned into the prescribed units in the different information processing apparatus, on the basis of storage area information that identifies data to which the target local data corresponds in the global data; and extracting as many pieces of local data as specified by the number of the continuous sections and transmitting the data to the different information processing apparatus.
摘要翻译：一种信息处理装置，在分配了一个本地数据的多个信息处理装置中，通过划分由多个信息处理装置共享的全局数据而获得的本地数据，包括：存储单元包括分为规定单位的第一存储区域，并存储本地数据; 执行处理的处理器，包括：基于存储区域信息，检测在不同信息处理设备中被划分为规定单元的第二存储区域中要写入目标本地数据的多个连续区段其识别目标本地数据在全局数据中对应的数据; 并且提取由连续段的数量指定的多条本地数据，并将数据发送到不同的信息处理设备。

50. 发明授权

US09330031B2 System and method for calibration of serial links using a serial-to-parallel loopback 有权
标题翻译：使用串行到并行环回校准串行链路的系统和方法
公开(公告)号：US09330031B2
公开(公告)日：2016-05-03
申请号：US13316386
申请日：2011-12-09
申请人： Alok Gupta
发明人： Alok Gupta
IPC分类号： G06F12/00 , G06F13/12 , G06F12/12 , G11C29/36
CPC分类号： G06F13/12 , G06F12/12 , G06F13/4234 , G11C2029/3602
摘要： A system and method for calibration of serial links using serial-to-parallel loopback. Embodiments of the present invention are operable for calibrating serial links using parallel links thereby reducing the number of links that need calibration. The method includes sending serialized data over a serial interface and receiving parallel data via a parallel interface. The serialized data is looped back via the parallel interface. The method further includes comparing the parallel data and the serialized data for a match thereof and calibrating the serial interface by adjusting the sending of the serialized data until the comparing detects the match. The adjusting of the sending is operable to calibrate the sending of the serialized data over the serial interface.
摘要翻译：一种使用串行到并行环回校准串行链路的系统和方法。本发明的实施例可用于使用并行链路校准串行链路，从而减少需要校准的链路的数量。该方法包括通过串行接口发送串行数据，并通过并行接口接收并行数据。序列化数据通过并行接口环回。该方法还包括比较并行数据和串行数据以进行匹配，并通过调整串行化数据的发送来校准串行接口，直到比较检测到匹配为止。发送的调整可以通过串行接口校准串行化数据的发送。

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