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1. 发明申请

US20140237205A1 SYSTEM AND METHOD FOR PROVIDING A COMMAND BUFFER IN A MEMORY SYSTEM 有权
标题翻译：用于在存储器系统中提供命令缓冲器的系统和方法
公开(公告)号：US20140237205A1
公开(公告)日：2014-08-21
申请号：US14265280
申请日：2014-04-29
申请人： Diablo Technologies Inc.
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： G06F3/06
CPC分类号： G06F3/0656 , G06F3/0604 , G06F3/065 , G06F3/0659 , G06F3/0683 , G06F11/1008 , G06F12/1027 , G06F13/1673 , G06F21/71 , G06F21/85 , G09C1/00 , H03M13/05 , H04L9/3073 , H04L2209/125
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system is configured to receive a command from a host memory controller of a host system and store the command in a command buffer entry. The system determines that the command is complete using a buffer check logic and provides the command to a command buffer. The command buffer comprises a first field that specifies an entry point of the command within the command buffer entry.
摘要翻译：公开了一种用于与协处理器或输入/输出设备进行接口的系统。根据一个实施例，系统被配置为从主机系统的主机存储器控制器接收命令，并将命令存储在命令缓冲器条目中。系统使用缓冲区检查逻辑确定命令完成，并向命令缓冲区提供命令。命令缓冲器包括指定命令缓冲器条目内的命令的入口点的第一字段。

2. 发明申请

US20160041933A1 SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER IN A COMPUTER SYSTEM 审中-公开
标题翻译：用于在计算机系统中实现多线程设备驱动器的系统和方法
公开(公告)号：US20160041933A1
公开(公告)日：2016-02-11
申请号：US14452473
申请日：2014-08-05
申请人： Diablo Technologies, Inc.
发明人： Bart Trojanowski , Michael L. Takefman , Maher Amer
IPC分类号： G06F13/362 , G06F9/44 , G06F9/30 , G06F9/50 , G06F13/42 , G06F13/366
CPC分类号： G06F13/3625 , G06F9/3009 , G06F9/4881 , G06F13/366 , G06F13/4221
摘要： A method of implementing a multi-threaded device driver for a computer system is disclosed. According to one embodiment, a polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread.
摘要翻译：公开了一种实现计算机系统的多线程设备驱动程序的方法。根据一个实施例，轮询设备驱动程序被划分成用于控制计算机系统的设备的多个驱动程序线程。该设备具有未协调状态和侦察状态的第一设备状态，以及处于非活动状态和活动状态的第二设备状态。多个驱动程序线程的驱动程序线程确定设备状态的第一设备状态处于未协调状态，并将设备的第一状态改变为侦察状态。驾驶员线程进一步确定设备的第二设备状态处于非活动状态，并将设备的第二设备状态改变为活动状态。在为驱动程序线程配置的预定时隙期间，驱动程序线程在设备上执行操作。

3. 发明申请

US20160041917A1 SYSTEM AND METHOD FOR MIRRORING A VOLATILE MEMORY OF A COMPUTER SYSTEM 审中-公开
标题翻译：用于模拟计算机系统的易失性存储器的系统和方法
公开(公告)号：US20160041917A1
公开(公告)日：2016-02-11
申请号：US14452477
申请日：2014-08-05
申请人： Diablo Technologies, Inc.
发明人： Bart Trojanowski , Maher Amer , Riccardo Badalone , Michael L. Takefman
IPC分类号： G06F12/08 , G06F3/06
CPC分类号： G06F3/068 , G06F11/1441
摘要： A system and method for mirroring a volatile memory to a CPIO device of a computer system is disclosed. According to one embodiment, a command buffer and a data buffer are provided to store data and a command for mirroring the data. The command specifies metadata associated with the data. The data is mirrored a non-volatile memory of the CPIO device based on the command.
摘要翻译：公开了一种用于将易失性存储器镜像到计算机系统的CPIO设备的系统和方法。根据一个实施例，提供命令缓冲器和数据缓冲器以存储数据和用于镜像数据的命令。该命令指定与数据相关联的元数据。该数据根据该命令镜像到CPIO设备的非易失性存储器。

4. 发明申请

US20150326684A1 SYSTEM AND METHOD OF ACCESSING AND CONTROLLING A CO-PROCESSOR AND/OR INPUT/OUTPUT DEVICE VIA REMOTE DIRECT MEMORY ACCESS 审中-公开
标题翻译：通过远程直接存储器访问来访问和控制协处理器和/或输入/输出设备的系统和方法
公开(公告)号：US20150326684A1
公开(公告)日：2015-11-12
申请号：US14271838
申请日：2014-05-07
申请人： Diablo Technologies Inc.
发明人： Michael L. Takefman , Bart Trojankowski , Maher Amer , Riccardo Badalone
IPC分类号： H04L29/08 , H04L29/06
CPC分类号： H04L67/125 , G06F9/54 , G06F13/00 , H04L67/2842 , H04L67/40
摘要： A method of controlling a remote computer device of a remote computer system over a remote direct memory access (RDMA) is disclosed. According to one embodiment, the method includes establishing a connection for remote direct memory access (RDMA) between a local memory device of a local computer system and a remote memory device of a remote computer system. A local command is sent from a local application that is running on the local computer system to the remote memory device of the remote computer system via the RDMA. The remote computer system executes the local command on the remote computer device.
摘要翻译：公开了一种通过远程直接存储器访问（RDMA）来控制远程计算机系统的远程计算机设备的方法。根据一个实施例，该方法包括在本地计算机系统的本地存储设备和远程计算机系统的远程存储设备之间建立用于远程直接存储器访问（RDMA）的连接。本地命令通过RDMA从本地计算机系统上运行的本地应用程序发送到远程计算机系统的远程存储设备。远程计算机系统在远程计算机设备上执行本地命令。

5. 发明申请

US20150309959A1 System and Method of Interfacing Co-Processors and Input/Output Devices via a Main Memory System 有权
标题翻译：通过主内存系统与协处理器和输入/输出设备进行接口的系统和方法
公开(公告)号：US20150309959A1
公开(公告)日：2015-10-29
申请号：US14635960
申请日：2015-03-02
申请人： Diablo Technologies Inc.
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： G06F13/42 , G06F11/10 , G06F9/44 , G06F12/02
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F9/4406 , G06F11/1016 , G06F11/1076 , G06F12/0246 , G06F12/0607 , G06F13/20 , G06F13/404 , G06F13/4221 , G06F13/4234 , G06F13/4282 , G06F2212/1008 , G06F2212/1032 , G06F2212/7201 , G06F2212/7208 , H03M13/05 , H03M13/27 , H04L9/0662
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
摘要翻译：公开了一种用于与协处理器或输入/输出设备进行接口的系统。根据一个实施例，系统包括计算机处理单元，存储器模块，连接计算机处理单元和存储器模块的存储器总线以及协处理单元或输入/输出设备，其中存储器总线还将协处理单元或输入/输出设备到计算机处理单元。

6. 发明申请

US20140237176A1 SYSTEM AND METHOD FOR UNLOCKING ADDITIONAL FUNCTIONS OF A MODULE 有权
标题翻译：用于解锁模块的附加功能的系统和方法
公开(公告)号：US20140237176A1
公开(公告)日：2014-08-21
申请号：US14265241
申请日：2014-04-29
申请人： Diablo Technologies Inc.
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： G06F13/16 , G06F13/40
CPC分类号： G06F13/1657 , G06F11/1008 , G06F12/0607 , G06F12/0646 , G06F13/404 , G06F21/629 , G06F21/85 , G06F2221/2147 , H03M13/05
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system performs a maze unlock sequence by operating a memory device in a maze unlock mode. The maze unlock sequence involves writing a first data pattern of a plurality of data patterns to a memory address of the memory device, reading a first set of data from the memory address, and storing the first set of data in a validated data array. The maze unlock sequence further involves writing a second data pattern of the plurality of data patterns to the memory address, reading a second set of data from the memory address, and storing the second set of data in the validated data array. A difference vector array is generated from the validate data array and an address map of the memory device is identified based on the difference vector array.
摘要翻译：公开了一种用于与协处理器或输入/输出设备进行接口的系统。根据一个实施例，系统通过在迷宫解锁模式中操作存储设备来执行迷宫解锁序列。迷宫解锁序列包括将多个数据模式的第一数据模式写入存储器件的存储器地址，从存储器地址读取第一组数据，并将第一组数据存储在经过验证的数据阵列中。迷宫解锁序列还包括将多个数据模式的第二数据模式写入存储器地址，从存储器地址读取第二组数据，并将第二组数据存储在经过验证的数据阵列中。从验证数据阵列生成差分矢量阵列，并且基于差分矢量阵列识别存储器件的地址映射。

7. 发明授权

US09575908B2 System and method for unlocking additional functions of a module 有权
标题翻译：解锁模块附加功能的系统和方法
公开(公告)号：US09575908B2
公开(公告)日：2017-02-21
申请号：US14265241
申请日：2014-04-29
申请人： Diablo Technologies Inc.
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： G06F12/06 , G06F11/10 , G06F13/16 , G06F13/40 , G06F21/62 , H03M13/05 , G06F21/85
CPC分类号： G06F13/1657 , G06F11/1008 , G06F12/0607 , G06F12/0646 , G06F13/404 , G06F21/629 , G06F21/85 , G06F2221/2147 , H03M13/05
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system performs a maze unlock sequence by operating a memory device in a maze unlock mode. The maze unlock sequence involves writing a first data pattern of a plurality of data patterns to a memory address of the memory device, reading a first set of data from the memory address, and storing the first set of data in a validated data array. The maze unlock sequence further involves writing a second data pattern of the plurality of data patterns to the memory address, reading a second set of data from the memory address, and storing the second set of data in the validated data array. A difference vector array is generated from the validate data array and an address map of the memory device is identified based on the difference vector array.
摘要翻译：公开了一种用于与协处理器或输入/输出设备进行接口的系统。根据一个实施例，系统通过在迷宫解锁模式中操作存储设备来执行迷宫解锁序列。迷宫解锁序列包括将多个数据模式的第一数据模式写入存储器件的存储器地址，从存储器地址读取第一组数据，并将第一组数据存储在经过验证的数据阵列中。迷宫解锁序列还包括将多个数据模式的第二数据模式写入存储器地址，从存储器地址读取第二组数据，并将第二组数据存储在经过验证的数据阵列中。从验证数据阵列生成差分矢量阵列，并且基于差分矢量阵列识别存储器件的地址映射。

8. 发明申请

US20150294698A1 System and Method for Offsetting The Data Buffer Latency of a Device Implementing a JEDEC Standard DDR-4 LRDIMM Chipset 有权
标题翻译：用于抵消实施JEDEC标准DDR-4 LRDIMM芯片组的设备的数据缓冲器延迟的系统和方法
公开(公告)号：US20150294698A1
公开(公告)日：2015-10-15
申请号：US14664580
申请日：2015-03-20
申请人： Diablo Technologies Inc.
发明人： Michael L. Takefman , Maher Amer , Claus Reitlinshoefer
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G06F13/1673 , G11C5/04 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093
摘要： A system and method for offsetting the data buffer latency in a CPIO device having a JEDEC standard DDR-4 LRDIMM chipset as the front end is disclosed. According to one embodiment, a CPIO ASIC provides variable timing control for its DDR-4 LRDIMM interface such that propagation delay of the data buffers can be offset by the CPIO ASIC, allowing the CPIO LRDIMM to be timing compatible with an RDIMM.
摘要翻译：公开了一种用于抵消具有JEDEC标准DDR-4 LRDIMM芯片组作为前端的CPIO设备中的数据缓冲器延迟的系统和方法。根据一个实施例，CPIO ASIC为其DDR-4 LRDIMM接口提供可变定时控制，使得数据缓冲器的传播延迟可被CPIO ASIC偏移，从而允许CPIO LRDIMM与RDIMM定时兼容。

9. 发明授权

US08972805B2 System and method of interfacing co-processors and input/output devices via a main memory system 有权
标题翻译：通过主存储器系统连接协处理器和输入/输出设备的系统和方法
公开(公告)号：US08972805B2
公开(公告)日：2015-03-03
申请号：US14247162
申请日：2014-04-07
申请人： Diablo Technologies Inc.
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： G06F11/00 , H03M13/00 , G06F13/20 , H03M13/05 , G06F11/10 , G06F12/02 , G06F12/06 , H04L9/06
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F9/4406 , G06F11/1016 , G06F11/1076 , G06F12/0246 , G06F12/0607 , G06F13/20 , G06F13/404 , G06F13/4221 , G06F13/4234 , G06F13/4282 , G06F2212/1008 , G06F2212/1032 , G06F2212/7201 , G06F2212/7208 , H03M13/05 , H03M13/27 , H04L9/0662
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
摘要翻译：公开了一种用于与协处理器或输入/输出设备进行接口的系统。根据一个实施例，系统包括计算机处理单元，存储器模块，连接计算机处理单元和存储器模块的存储器总线以及协处理单元或输入/输出设备，其中存储器总线还将协处理单元或输入/输出设备到计算机处理单元。

10. 发明申请

US20140223262A1 System and Method of Interfacing Co-Processors and Input/Output Devices via a Main Memory System 有权
标题翻译：通过主内存系统与协处理器和输入/输出设备进行接口的系统和方法
公开(公告)号：US20140223262A1
公开(公告)日：2014-08-07
申请号：US14247162
申请日：2014-04-07
申请人： Diablo Technologies Inc.
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： G06F13/20 , H04L9/06 , G06F12/02 , G06F11/10 , G06F12/06
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F9/4406 , G06F11/1016 , G06F11/1076 , G06F12/0246 , G06F12/0607 , G06F13/20 , G06F13/404 , G06F13/4221 , G06F13/4234 , G06F13/4282 , G06F2212/1008 , G06F2212/1032 , G06F2212/7201 , G06F2212/7208 , H03M13/05 , H03M13/27 , H04L9/0662
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
摘要翻译：公开了一种用于与协处理器或输入/输出设备进行接口的系统。根据一个实施例，系统包括计算机处理单元，存储器模块，连接计算机处理单元和存储器模块的存储器总线以及协处理单元或输入/输出设备，其中存储器总线还将协处理单元或输入/输出设备到计算机处理单元。

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