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1. 发明申请

US20170102873A1 DIMM SSD ADDRESSING PERFORMANCE TECHNIQUES 审中-公开
公开(公告)号：US20170102873A1
公开(公告)日：2017-04-13
申请号：US15060596
申请日：2016-03-03
申请人： Craig HANSON , Ian SWARBRICK , Michael BEKERMAN , Chihjen CHANG
发明人： Craig HANSON , Ian SWARBRICK , Michael BEKERMAN , Chihjen CHANG
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F12/0638
摘要： A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM) (105). The NVDIMM (105) may be installed in a Dual In-Line Memory Module (DIMM) docket (125). The NVDIMM (105) may include a non-volatile memory (130). A device driver (160) may intercept a request for a memory address (605) destined for a host memory controller (115), replace the memory address (605) with a pre-mapped memory address (610) or an alias (705, 710) of the pre-mapped memory address (610), and send the pre-mapped memory address (610) to the host memory controller (115), so that the host memory controller (115) generates a target memory address (615) to NVDIMM (105).

2. 发明授权

US10025747B2 I/O channel scrambling/ECC disassociated communication protocol 有权
公开(公告)号：US10025747B2
公开(公告)日：2018-07-17
申请号：US14967258
申请日：2015-12-11
申请人： Ian Swarbrick , Michael Bekerman , Craig Hanson , Chihjen Chang
发明人： Ian Swarbrick , Michael Bekerman , Craig Hanson , Chihjen Chang
IPC分类号： G06F13/38 , G06F13/42
摘要： A protocol that enables communication between a host and an Input/Output (I/O) channel storage device, such as a Dynamic Random Access Memory (DRAM) channel Dual In-Line Memory Module (DIMM) form-factor Solid State Drive (SSD), without the need to know or reverse engineer the encoding applied by the host. The control/status data are written to the storage device by sending a protocol training sequence of known values and storing the associated command/status data in the storage device in the same encoding format as that received from the host. These stored values are used at run time to execute encoded commands received from the host and to report status data to the host in the host-recognizable manner. A memory bank-based buffered configuration stores user data also in the as-received condition to preserve the host-specific encoding. This facilitates exchange of user data between the host memory controller and the storage device over the DRAM channel.

3. 发明申请

US20160328156A1 DRAM MEMORY CHANNEL SCRAMBLING/ECC DISASSOCIATED COMMUNICATION 有权
标题翻译： DRAM存储器通道SCRAMBLING / ECC DISASSOCIATED COMMUNICATION
公开(公告)号：US20160328156A1
公开(公告)日：2016-11-10
申请号：US14967258
申请日：2015-12-11
申请人： Ian SWARBRICK , Michael BEKERMAN , Craig HANSON , Chihjen CHANG
发明人： Ian SWARBRICK , Michael BEKERMAN , Craig HANSON , Chihjen CHANG
IPC分类号： G06F3/06
CPC分类号： G06F13/4234
摘要： A protocol that enables communication between a host and an Input/Output (I/O) channel storage device, such as a Dynamic Random Access Memory (DRAM) channel Dual In-Line Memory Module (DIMM) form-factor Solid State Drive (SSD), without the need to know or reverse engineer the encoding applied by the host. The control/status data are written to the storage device by sending a protocol training sequence of known values and storing the associated command/status data in the storage device in the same encoding format as that received from the host. These stored values are used at run time to execute encoded commands received from the host and to report status data to the host in the host-recognizable manner. A memory bank-based buffered configuration stores user data also in the as-received condition to preserve the host-specific encoding. This facilitates exchange of user data between the host memory controller and the storage device over the DRAM channel.
摘要翻译：支持主机与输入/输出（I / O）通道存储设备之间的通信的协议，例如动态随机存取存储器（DRAM）通道双列直插存储器模块（DIMM）外形固态驱动器（SSD）），而不需要知道或逆向工程主机应用的编码。控制/状态数据通过发送已知值的协议训练序列并以与从主机接收的编码格式相同的编码格式将相关联的命令/状态数据存储在存储设备中而被写入存储设备。在运行时使用这些存储的值来执行从主机接收的编码命令，并以主机可识别的方式将状态数据报告给主机。基于存储体的缓冲配置也将用户数据也存储在接收状态以保存主机特定的编码。这有助于通过DRAM信道在主机存储器控制器和存储设备之间交换用户数据。

4. 发明授权

US07290162B2 Clock distribution system 有权
标题翻译：时钟分配系统
公开(公告)号：US07290162B2
公开(公告)日：2007-10-30
申请号：US10468168
申请日：2002-02-14
申请人： Ian Swarbrick , David Williams
发明人： Ian Swarbrick , David Williams
IPC分类号： G06F1/00 , G06F9/45
CPC分类号： H04L45/00 , G06F1/10 , G06F15/8007 , G06F17/505 , H04L12/56 , H04L45/742 , Y10S707/99936
摘要： A clock distribution system for an integrated circuit comprising a plurality of regions (1, 2, 3) connected by a communications bus (12). Each region comprises a functional block (10a, 10b, 10c) and at least one bus node (14a, 14b, 14c) for connecting a respective functional block to the communications bus (12). A distributed clock signal (16) is allowed to skew between regions, but synchronised within respective regions. A predetermined clock insertion delay (20a, 20b, 20c, 22a, 22b, 22c) is inserted in each functional block and bus node.
摘要翻译：一种用于集成电路的时钟分配系统，包括由通信总线（12）连接的多个区域（1,2,3）。每个区域包括用于将相应的功能块连接到通信总线（12）的功能块（10a，10b，10b）和至少一个总线节点（14a，14b，14c）。允许分布式时钟信号（16）在区域之间偏斜，但在相应区域内同步。预定的时钟插入延迟（20 a，20 b，20 c，22 a，22 b，22 c）插入每个功能块和总线节点。

5. 发明授权

US10031674B2 DIMM SSD addressing performance techniques 有权
公开(公告)号：US10031674B2
公开(公告)日：2018-07-24
申请号：US15060596
申请日：2016-03-03
申请人： Craig Hanson , Ian Swarbrick , Michael Bekerman , Chihjen Chang
发明人： Craig Hanson , Ian Swarbrick , Michael Bekerman , Chihjen Chang
IPC分类号： G06F12/00 , G06F3/06
摘要： A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM) (105). The NVDIMM (105) may be installed in a Dual In-Line Memory Module (DIMM) docket (125). The NVDIMM (105) may include a non-volatile memory (130). A device driver (160) may intercept a request for a memory address (605) destined for a host memory controller (115), replace the memory address (605) with a pre-mapped memory address (610) or an alias (705, 710) of the pre-mapped memory address (610), and send the pre-mapped memory address (610) to the host memory controller (115), so that the host memory controller (115) generates a target memory address (615) to NVDIMM (105).

6. 发明授权

US08448001B1 System having a first device and second device in which the main power management module is configured to selectively supply a power and clock signal to change the power state of each device independently of the other device 有权
标题翻译：具有第一设备和第二设备的系统，其中主电源管理模块被配置为选择性地提供电源和时钟信号以独立于其他设备改变每个设备的电源状态
公开(公告)号：US08448001B1
公开(公告)日：2013-05-21
申请号：US12715612
申请日：2010-03-02
申请人： Jun Zhu , Ian Swarbrick , Joseph Jun Cao , Sheng Lu , Pantas Sutardja
发明人： Jun Zhu , Ian Swarbrick , Joseph Jun Cao , Sheng Lu , Pantas Sutardja
IPC分类号： G06F1/00 , G06F1/32 , G06F1/26
CPC分类号： G06F1/3206 , G06F1/3209 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A system includes a first device, a second device, and a main power management module. The first device is configured to communicate with a system bus. The second device is configured to communicate with the system bus. The second device includes a device power management module configured to manage power states of the second device. The main power management module is configured to manage power consumption of the second device independently of the first device by selectively supplying power and clock signals to the second device based on the power states of the second device. The main power management module and the device power management module each comprise a power handshake interface. The main power management module communicates with the device power management module via a power management bus using the power handshake interface.
摘要翻译：系统包括第一设备，第二设备和主电源管理模块。第一个设备被配置为与系统总线进行通信。第二个设备被配置为与系统总线进行通信。第二设备包括被配置为管理第二设备的电源状态的设备电源管理模块。主电源管理模块被配置为基于第二设备的电源状态选择性地向第二设备提供电力和时钟信号来管理与第一设备无关的功率消耗。主电源管理模块和设备电源管理模块各自包括电源握手接口。主电源管理模块通过使用电源握手接口的电源管理总线与设备电源管理模块进行通信。

7. 发明授权

US08378738B1 Adaptive voltage scaling using a delay line 有权
标题翻译：使用延迟线进行自适应电压调整
公开(公告)号：US08378738B1
公开(公告)日：2013-02-19
申请号：US12899813
申请日：2010-10-07
申请人： Jun Zhu , Joseph Jun Cao , Ian Swarbrick
发明人： Jun Zhu , Joseph Jun Cao , Ian Swarbrick
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K5/24 , G06F1/3296 , H03K5/26 , Y02D10/172
摘要： In one embodiment, a method includes determining, for an integrated circuit chip, a delay measurement corresponding to a first number of stages in a delay line. A power supply voltage measurement is also determined. The method determines a second number of stages correlated to the power supply voltage measurement. The second number of stages correspond to a desired timing delay. It is determined if a power supply voltage should be adjusted using a comparison based on the first number of stages and the second number of stages. A control signal is output for adjusting the power supply voltage when it is determined the power supply voltage should be adjusted.
摘要翻译：在一个实施例中，一种方法包括针对集成电路芯片确定对应于延迟线中的第一级的延迟测量。还确定电源电压测量。该方法确定与电源电压测量相关的第二级数。第二级数对应于期望的定时延迟。确定是否应该使用基于第一级数和第二级数的比较来调整电源电压。输出控制信号，以便在确定应调整电源电压时调节电源电压。

8. 发明申请

US20070083831A1 Various methods and apparatuses for estimating characteristics of an electronic system's design 有权
标题翻译：用于估计电子系统设计特征的各种方法和装置
公开(公告)号：US20070083831A1
公开(公告)日：2007-04-12
申请号：US11398036
申请日：2006-04-04
申请人： Stephen Hamilton , Ian Swarbrick , Scott Evans , Wolf-Dietrich Weber , Jay Tomlinson
发明人： Stephen Hamilton , Ian Swarbrick , Scott Evans , Wolf-Dietrich Weber , Jay Tomlinson
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045 , G06F17/50 , G06F2217/78 , G06F2217/84
摘要： Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.
摘要翻译：描述了用于估计电子系统设计的时间，面积和功率特性的知识产权（IP）发生器的方法和装置。 IP生成器接收用户提供的文件，该文件具有描述具有多层次结构的IP设计的配置的数据。 IP生成器还接收用户提供的技术参数和数据流信息。 IP生成器根据用户提供的技术参数，数据流信息和配置参数，关联每个IP子组件的估计时序，面积和功率特性。在将寄存器传输级别（RTL）设计转换为门级电路设计之前，IP生成器通过图形用户界面向用户报告定时，面积和功率估计。

9. 发明申请

US20070083830A1 Various methods and apparatuses for an executable parameterized timing model 审中-公开
标题翻译：用于可执行参数化定时模型的各种方法和装置
公开(公告)号：US20070083830A1
公开(公告)日：2007-04-12
申请号：US11246809
申请日：2005-10-07
申请人： Stephen Hamilton , Ian Swarbrick , Scott Evans , Wolf-Dietrich Weber , Jay Tomlinson
发明人： Stephen Hamilton , Ian Swarbrick , Scott Evans , Wolf-Dietrich Weber , Jay Tomlinson
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045 , G06F2217/78 , G06F2217/84
摘要： Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area and power constraints in an electronic design system. The IP Generator receives a user-supplied file having data describing a configuration of an intellectual property (IP) design, the data includes one or more configuration parameters. The IP Generator further enables a transformation of the user-supplied file into a register transfer level design description. Next, the IP Generator receives user-supplied technology parameters and data-flow information. The technology parameters describe a configuration of the IP design. Next, the IP Generator executes a timing module based on the configuration of the IP design as well as executes a timing model for each hierarchical level in the IP design. The timing model predicts timing paths of a final logic circuit. Further, a result of the timing model is provided to the user prior to enabling a transformation of a register transfer level design into the simulation of a gate-level circuit design. Lastly, after the timing model has been executed, is the enablement of the transformation of the register transfer level design into the simulation of the gate-level circuit design.
摘要翻译：描述了用于估计电子设计系统中的时间，面积和功率约束的知识产权（IP）发生器的方法和装置。 IP生成器接收具有描述知识产权（IP）设计的配置的数据的用户提供的文件，该数据包括一个或多个配置参数。 IP生成器还可以将用户提供的文件转换为注册传输级设计描述。接下来，IP生成器接收用户提供的技术参数和数据流信息。技术参数描述了IP设计的配置。接下来，IP生成器基于IP设计的配置执行定时模块，并且为IP设计中的每个层级执行定时模型。定时模型预测最终逻辑电路的定时路径。此外，在将寄存器传送级别设计转换为门级电路设计的仿真之前，将定时模型的结果提供给用户。最后，在执行定时模型之后，将寄存器传输级设计的转换实现为门级电路设计的仿真。

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