专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20040088472A1 Multi-mode memory controller 审中-公开
标题翻译：多模式存储控制器
公开(公告)号：US20040088472A1
公开(公告)日：2004-05-06
申请号：US10284869
申请日：2002-10-31
发明人： John M. Nystuen , Sandeep J. Sathe
IPC分类号： G06F012/00
CPC分类号： G06F13/1647
摘要： A memory controller is provided, which includes a request input for receiving successive memory access requests and a memory interface configured for coupling to a memory device having a plurality of banks. The memory controller has a bank control circuit, which generates a bank access command on the memory interface for a respective one of the banks in response to each memory access request to that bank. The bank control circuit has a plurality of selectable operating modes, including a Request Count Mode. When in the Request Count Mode, the bank control circuit generates a bank precharge command on the memory interface for the respective bank if none of a predetermined number of subsequent ones of the memory access requests is to that bank.
摘要翻译：提供了一种存储器控制器，其包括用于接收连续存储器访问请求的请求输入和被配置为耦合到具有多个存储体的存储器件的存储器接口。存储器控制器具有存储体控制电路，其响应于对该存储体的每个存储器访问请求，针对相应的一个存储体在存储器接口上生成存储体访问命令。银行控制电路具有多个可选择的操作模式，包括请求计数模式。当处于请求计数模式时，如果存储器访问请求中的预定数量的存储器访问请求中的任何一个都不是该存储体，则存储体控制电路在相应存储体的存储器接口上产生存储体预充电命令。

42. 发明授权

US06725314B1 Multi-bank memory subsystem employing an arrangement of multiple memory modules 有权
标题翻译：采用多个存储器模块布置的多存储存储器子系统
公开(公告)号：US06725314B1
公开(公告)日：2004-04-20
申请号：US09823540
申请日：2001-03-30
申请人： Lam S. Dong
发明人： Lam S. Dong
IPC分类号： G06F1300
CPC分类号： G06F13/1684 , G06F13/1647 , G06F13/409
摘要： A multi-bank memory subsystem employing multiple memory modules. A memory subsystem includes a memory controller coupled to a memory bus. The memory bus includes a plurality of data paths each corresponding to a separate grouping of data lines. The memory bus is coupled to a first plurality of memory modules corresponding to a first memory bank. The first memory bank corresponding to a first range of addresses. The memory bus is also coupled to a second plurality of memory modules corresponding to a second memory bank. The second memory bank corresponding to a second range of addresses. A separate memory module of each of the first and the second memory banks is coupled to each data path of the memory bus. Memory modules that are coupled to the same data path are located adjacent to one another without any intervening memory modules coupled to other data paths.
摘要翻译：采用多个存储器模块的多存储存储器子系统。存储器子系统包括耦合到存储器总线的存储器控制器。存储器总线包括多个数据路径，每个对应于数据线的单独分组。存储器总线耦合到对应于第一存储体的第一多个存储器模块。第一存储体对应于第一范围的地址。存储器总线还耦合到对应于第二存储体的第二多个存储器模块。第二存储体对应于第二范围的地址。第一和第二存储器组中的每一个的单独存储器模块耦合到存储器总线的每个数据路径。耦合到相同数据路径的存储器模块彼此相邻定位，而没有任何中间存储器模块耦合到其他数据路径。

43. 发明授权

US06721229B1 Method and apparatus for using SDRAM to read and write data without latency 有权
标题翻译：使用SDRAM读取和写入数据而无延迟的方法和装置
公开(公告)号：US06721229B1
公开(公告)日：2004-04-13
申请号：US10160664
申请日：2002-05-31
申请人： Philip D. Cole
发明人： Philip D. Cole
IPC分类号： G11C800
CPC分类号： G11C7/1042 , G06F13/1647
摘要： An apparatus and method are provided for transmitting data using synchronous dynamic random access memory (SDRAM). In example, the method includes writes data using a first set of SDRAM banks. Data is written using a second set of SDRAM banks, wherein the first set of SDRAM banks and the second set of SDRAM banks write interleaved, Data is read using a third set of SDRAM banks. Data is read using a fourth set of SDRAM banks, wherein the fourth set of SDRAM banks and the third set of SDRAM banks read interleaved.
摘要翻译：提供了一种用于使用同步动态随机存取存储器（SDRAM）发送数据的装置和方法。例如，该方法包括使用第一组SDRAM存储体的写入数据。使用第二组SDRAM库写入数据，其中第一组SDRAM存储体和第二组SDRAM存储体写入交错，使用第三组SDRAM存储体读取数据。使用第四组SDRAM存储体读取数据，其中第四组SDRAM存储体和第三组SDRAM存储体读取交织。

44. 发明申请

US20030196058A1 Memory system for supporting multiple parallel accesses at very high frequencies 有权
标题翻译：用于以非常高的频率支持多个并行访问的存储器系统
公开(公告)号：US20030196058A1
公开(公告)日：2003-10-16
申请号：US10120686
申请日：2002-04-11
发明人： Hebbalalu S. Ramagopal , Murali S. Chinnakonda , Thang M. Tran
IPC分类号： G06F012/00
CPC分类号： G11C7/10 , G06F13/1615 , G06F13/1647
摘要： A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, and a memory control unit for processing access requests from the processor, from the store buffer and from the load buffer. The memory control unit may include prioritization logic for selecting access requests in accordance with a priority scheme and bank conflict logic for detecting and handling conflicts between access requests. The pipelined memory may be configured to output two load results per clock cycle at very high speed.
摘要翻译：用于与处理器（例如数字信号处理器）一起操作的存储器系统包括高速流水线存储器，用于保存来自处理器的存储访问请求的存储缓冲器，用于保存来自处理器的加载访问请求的加载缓冲器和存储器控制单元，用于处理来自处理器，存储缓冲器和加载缓冲器的访问请求。存储器控制单元可以包括用于根据优先级方案选择访问请求的优先化逻辑和用于检测和处理访问请求之间的冲突的库冲突逻辑。流水线存储器可以被配置为以非常高的速度在每个时钟周期输出两个负载结果。

45. 发明申请

US20030115403A1 Dynamic random access memory system with bank conflict avoidance feature 有权
标题翻译：具有银行冲突避免功能的动态随机存取存储系统
公开(公告)号：US20030115403A1
公开(公告)日：2003-06-19
申请号：US10025331
申请日：2001-12-19
发明人： Gregg A. Bouchard , Mauricio Calle , Ravi Ramaswami
IPC分类号： G06F012/00
CPC分类号： G06F13/1647 , Y02D10/14
摘要： A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks operatively coupled to the memory controller, with each of the memory banks configured for storing a plurality of data items. More particularly, a given data item is stored as multiple copies of the data item with a given one of the multiple copies in each of a designated minimum number of the memory banks. The memory controller is adapted to process requests for access to the data items stored in the memory banks in accordance with a specified bank access sequence. The minimum number of memory banks for storage of the multiple copies of the given data item may be determined as a function of a random cycle time and a random bank access delay of the memory banks, e.g., as an integer greater than or equal to a ratio of the random cycle time to the random bank access delay. The memory system is preferably operable in the above-described bank conflict avoidance mode as well as a standard random access mode. The memory system is particularly well-suited for use in an application involving an unbalanced ratio of read and write accesses, e.g., as an external tree memory for a network processor integrated circuit, but can also be used in numerous other processing device memory applications.
摘要翻译：具有多个存储体的存储器系统被配置为防止存取请求之间的存储体冲突。存储器系统包括存储器控制器和可操作地耦合到存储器控制器的多个存储器组，其中每个存储器组被配置用于存储多个数据项。更具体地，给定数据项被存储为具有指定的最小数量的存储体的每一个中的多个副本中的给定的一个的数据项的多个副本。存储器控制器适于根据指定的存储体访问顺序处理存储在存储体中的数据项的访问请求。用于存储给定数据项的多个副本的存储体的最小数量可以被确定为存储体的随机循环时间和随机存储体存取延迟的函数，例如，作为大于或等于随机周期时间与随机银行访问延迟的比率。存储器系统优选地可以在上述的库冲突避免模式以及标准随机存取模式中操作。存储器系统特别适用于涉及读和写访问不平衡比例的应用，例如作为用于网络处理器集成电路的外部树存储器，但也可用于许多其它处理设备存储器应用中。

46. 发明申请

US20030056056A1 Rambus dynamic random access memory 失效
标题翻译： Rambus动态随机存取存储器
公开(公告)号：US20030056056A1
公开(公告)日：2003-03-20
申请号：US10238186
申请日：2002-09-10
发明人： Nak Kyu Park
IPC分类号： G06F012/00
CPC分类号： G11C7/1087 , G06F13/1647 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C2207/229 , Y02D10/14
摘要： Disclosed is a Rambus DRAM capable of reducing power consumption and layout area by enabling data read/write control signal of accessed memory bank only, in a top memory bank and a bottom memory bank. The disclosed comprises: a top and a bottom memory bank blocks including a plurality of unit memory banks, respectively; and a data read/write control signal generation block for generating a top data write control signal and a top data read control signal to the top memory bank block and a bottom data write control signal and a bottom data read control signal to the bottom memory bank block, thereby controlling the top memory bank block and the bottom memory bank block to separately operate in data read/write operations.
摘要翻译：公开了一种Rambus DRAM，其能够通过仅在顶部存储体和底部存储体中实现访问存储体的数据读/写控制信号来降低功耗和布局面积。所公开的包括：分别包括多个单元存储体的顶部和底部存储体块; 以及数据读/写控制信号产生块，用于产生顶部存储体块的顶部数据写入控制信号和顶部数据读取控制信号，并将底部数据写入控制信号和底部数据读取控制信号发送到底部存储体从而控制顶部存储体块和底部存储体块以在数据读/写操作中单独操作。

47. 发明授权

US06418077B1 Memory access methods and devices for use with random access memories 有权
标题翻译：用于随机存取存储器的存储器访问方法和设备
公开(公告)号：US06418077B1
公开(公告)日：2002-07-09
申请号：US09192488
申请日：1998-11-17
申请人： Finbar Naven
发明人： Finbar Naven
IPC分类号： G11C800
CPC分类号： G06F13/1647 , G06F12/0607 , G11C7/1039 , G11C7/1042 , G11C8/12 , G11C11/409
摘要： In a memory access method used with a synchronous dynamic random access memory (SDRAM) having first and second banks, each information item is allocated respective first and second storage locations in the memory. The first and second storage locations are in the first and second banks (Bank 0, Bank 1) respectively. When, in the same time slot, it is required to write a first such information item (W) in the memory and to read a second such information item (R) from the memory, it is firstly determined which of the first and second banks currently holds the second information item (R). The first information item (W) is written in the first storage location allocated thereto if the determined bank is the second bank and is written in the second storage location allocated thereto if the determined bank is the first bank. The second information item (R) is read from the determined bank after the first information is written. As a result, the write and read operations can be interleaved, providing increasing throughput as is desirable in, for example, pipelined memory access systems. Other SDRAM access methods and devices for improving throughput are also disclosed, and the methods and devices are applicable more generally to other kinds of random access memory system including static RAMs and disk storage systems.
摘要翻译：在与具有第一和第二存储体的同步动态随机存取存储器（SDRAM）一起使用的存储器访问方法中，每个信息项目被分配在存储器中的相应的第一和第二存储位置。第一和第二存储位置分别在第一和第二存储体（存储体0，存储体1）中。当在相同的时隙中需要在存储器中写入第一个这样的信息项（W）并读取首先确定当前第一和第二存储体中的哪个存储第二信息项（R）的第二信息项（R）。如果确定的银行是第二银行，则第一信息项（W）被写入分配给它的第一存储位置，并且如果确定的银行是第一存储体，则被写入分配给它的第二存储位置。在写入第一信息之后，从确定的存储体读取第二信息项目（R）。结果，可以对写入和读取操作进行交织，从而提供在例如流水线存储器存取系统中所希望的增加的吞吐量。另外还公开了用于提高吞吐量的SDRAM访问方法和设备，并且该方法和设备更一般地适用于包括静态RAM和磁盘存储系统的其他种类的随机存取存储器系统。

48. 发明授权

US06340973B1 Memory control unit and memory control method and medium containing program for realizing the same 有权
标题翻译：存储器控制单元和存储器控制方法以及包含用于实现该程序的介质
公开(公告)号：US06340973B1
公开(公告)日：2002-01-22
申请号：US09244036
申请日：1999-02-04
申请人： Toshiyuki Ochiai , Yosuke Furukawa , Yutaka Tanaka , Kozo Kimura , Makoto Hirai , Tokuzo Kiyohara , Hideshi Nishida
发明人： Toshiyuki Ochiai , Yosuke Furukawa , Yutaka Tanaka , Kozo Kimura , Makoto Hirai , Tokuzo Kiyohara , Hideshi Nishida
IPC分类号： G06F13372
CPC分类号： G06F13/1647 , G11C7/1072 , G11C7/22
摘要： A transfer-target unit outputs commands for data reading and data writing. An address generator generates control signals in accordance with the commands, and outputs the number of bytes of data first transferred by read access. A command generator generates control commands in accordance with the control signals to control an SDRAM. At this time the command generator judges the number of transferred bytes to control so that the SDRAM executes instructions in order from an instruction which is the most efficient in data transfer. That is, in the case where data is read across a bank boundary, the command generator judges which is to be executed first between read processing in a bank 0 and active processing in a bank1, to control the SDRAM. A data processor mediates data transfer between the transfer-target unit and the SDRAM in accordance with the control commands. In this way, it is possible to issue commands so as to terminate data transfer in the minimum number of cycles in the case where data read processing is continuously performed to different banks. The number of cycles required for two continuous access (access to the bank 0 and the bank 1) can be thus reduced, thereby increasing effective transfer rates of the SDRAM.
摘要翻译：传输目标单元输出用于数据读取和数据写入的命令。地址生成器根据命令生成控制信号，并输出通过读取访问首先传送的数据的字节数。命令发生器根据控制信号产生控制命令以控制SDRAM。此时，命令生成器判断要进行控制的传送字节数，使得SDRAM从数据传输中最有效的指令按顺序执行指令。也就是说，在通过存储体边界读取数据的情况下，命令生成器判断在存储体0中的读取处理和存储体1中的有效处理之间首先执行哪个，以控制SDRAM。数据处理器根据控制命令介入转移目标单元和SDRAM之间的数据传输。以这种方式，可以发出命令，以便在数据读取的情况下以最小数量的周期终止数据传输不断对不同的银行进行处理。因此可以减少两次连续访问（对存储体0和存储体1的访问）所需的周期数，从而增加SDRAM的有效传输速率。

49. 发明授权

US6145063A Memory system and information processing system 失效
标题翻译：内存系统和信息处理系统
公开(公告)号：US6145063A
公开(公告)日：2000-11-07
申请号：US120730
申请日：1998-07-23
申请人： Kiyoji Ueno , Nobuyuki Ikumi
发明人： Kiyoji Ueno , Nobuyuki Ikumi
IPC分类号： G11C11/407 , G06F12/02 , G06F12/06 , G06F13/16 , G11C11/401 , G06F12/00
CPC分类号： G06F12/0215 , G06F12/0607 , G06F13/1631 , G06F13/1647 , Y02B60/1225 , Y02B60/1228
摘要： In a memory composed of a plurality of banks, even if succeeding access is performed to the same bank as that being currently accessed, the succeeding access can be controlled according to the destination which is currently accessed and its accessed state. In addition, if particular relationships exist between a precedingly accessed destination and the succeedingly accessed destination, a corresponding main word line out of main word lines which correspond to respective rows of respective banks can be still held in its selected state even after the preceding access has been terminated.
摘要翻译：在由多个存储体组成的存储器中，即使对与当前访问的同一个存储体进行成功的访问，也可以根据当前访问的目的地及其访问状态来控制后续访问。此外，如果在先前访问的目的地和随后访问的目的地之间存在特定的关系，则即使在先前访问之后，对应于相应行的各行的主字线中的对应主字线仍然可以保持在其选择的状态已被终止。

50. 发明授权

US5761731A Method and apparatus for performing atomic transactions in a shared memory multi processor system 失效
标题翻译：在共享存储器多处理器系统中执行原子事务的方法和装置
公开(公告)号：US5761731A
公开(公告)日：1998-06-02
申请号：US859462
申请日：1997-05-19
申请人： Stephen R. Van Doren , Denis Foley , David M. Fenwick
发明人： Stephen R. Van Doren , Denis Foley , David M. Fenwick
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/1647
摘要： A mechanism for ensuring the accurate and timely completion of atomic transactions by multiple nodes coupled to a memory via a common interconnect in a multiprocessor system includes a plurality of nodes coupled to a bus, the plurality of nodes including memory nodes, I/O nodes, and processor nodes. The memory nodes are each apportioned into a plurality of banks and together comprise the memory. Associated with each bank is a busy signal, indicating the availability of the bank of memory for transactions. A node may issue an atomic transaction to a block of memory data through the use of READ.sub.-- BANK.sub.-- LOCK and WRITE.sub.-- BANK.sub.-- UNLOCK instructions. The node executing the atomic transaction monitors the state of the busy signals of the banks, and when the bank is available, the node issues a READ.sub.-- BANK.sub.-- LOCK instruction, which sets the busy bit to indicate the unavailability of the bank. Upon the completion of the READ.sub.-- BANK.sub.-- LOCK instruction, the node issues a WRITE.sub.-- BANK.sub.-- UNLOCK instruction. The WRITE.sub.-- BANK.sub.-- UNLOCK instruction updates memory with the modified data and the bank busy bit is set to indicate availability of the bank to other nodes on the bus.
摘要翻译：用于确保通过多处理器系统中的公共互连耦合到存储器的多个节点准确和及时地完成原子事务的机制包括耦合到总线的多个节点，所述多个节点包括存储器节点，I / O节点，和处理器节点。存储器节点分别分配成多个存储体并且一起构成存储器。与每个银行相关联的是一个繁忙的信号，指示存储器的可用性用于交易。节点可以通过使用READ-BANK-LOCK和WRITE-BANK-UNLOCK指令向存储器数据块发出原子事务。执行原子事务的节点监视银行的忙信号的状态，并且当银行可用时，节点发出READ-BANK-LOCK指令，其将忙位设置为指示银行的不可用性。 READ-BANK-LOCK指令完成后，节点发出WRITE-BANK-UNLOCK指令。 WRITE-BANK-UNLOCK指令用修改后的数据更新存储器，并将存储区忙位设置为指示存储体对总线上其他节点的可用性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式