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1. 发明授权

US06944738B2 Scalable design for DDR SDRAM buses 有权
标题翻译： DDR SDRAM总线的可扩展设计
公开(公告)号：US06944738B2
公开(公告)日：2005-09-13
申请号：US10123398
申请日：2002-04-16
申请人： Lam S. Dong
发明人： Lam S. Dong
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1689
摘要： A memory subsystem and a method for use in accessing a memory system are disclosed. The memory subsystem comprising a plurality of SDRAM memory modules and a memory controller. The memory controller is capable of waiting to generate a memory clock signal for each of the SDRAM memory modules until a valid window for a control signal and an address signal; generating the memory clock signals during the valid window, and generating the control and address signals. The method comprises: waiting for a valid window for a control signal and an address signal; generating a memory clock during the valid window; and generating the control signal and the command signal a predetermined period of time after generating the memory clock signal.
摘要翻译：公开了一种存储器子系统和用于访问存储器系统的方法。存储器子系统包括多个SDRAM存储器模块和存储器控制器。存储器控制器能够等待为每个SDRAM存储器模块生成存储器时钟信号，直到控制信号和地址信号的有效窗口为止; 在有效窗口期间产生存储器时钟信号，并产生控制和地址信号。该方法包括：等待控制信号和地址信号的有效窗口; 在有效窗口期间产生存储器时钟; 以及在产生所述存储器时钟信号之后的预定时间段生成所述控制信号和所述命令信号。

2. 发明授权

US06721185B2 Memory module having balanced data I/O contacts pads 有权
标题翻译：具有平衡数据I / O接口焊盘的存储器模块
公开(公告)号：US06721185B2
公开(公告)日：2004-04-13
申请号：US09846873
申请日：2001-05-01
申请人： Lam S. Dong , Drew G. Doblar
发明人： Lam S. Dong , Drew G. Doblar
IPC分类号： H05K100
CPC分类号： G11C5/06 , H01L23/50 , H01L2924/0002 , H05K1/0219 , H05K1/117 , H05K2201/10159 , H01L2924/00
摘要： A memory module having balanced data input/output contacts. A memory module includes a printed circuit board having an edge connector and a plurality of memory integrated circuits. The edge connector may be adapted for insertion into a socket of a motherboard of a computer system, for example. The edge connector includes a plurality of contact pads on both sides of the printed circuit board. The contact pads are configured to convey data signals, power and ground to and from the printed circuit board. The power and ground contact pads alternate along the edge connector. There are no more than four data signal contact pads without intervening power or ground contact pads.
摘要翻译：具有平衡数据输入/输出触点的存储器模块。存储器模块包括具有边缘连接器和多个存储器集成电路的印刷电路板。边缘连接器可以适于例如插入到计算机系统的主板的插座中。边缘连接器包括在印刷电路板的两侧上的多个接触焊盘。接触焊盘被配置为将数据信号，电源和接地传送到印刷电路板和从印刷电路板传送。电源和接地触点垫沿着边缘连接器交替。没有多于四个数据信号接触焊盘，没有插入电源或接地触点。

3. 发明授权

US06725314B1 Multi-bank memory subsystem employing an arrangement of multiple memory modules 有权
标题翻译：采用多个存储器模块布置的多存储存储器子系统
公开(公告)号：US06725314B1
公开(公告)日：2004-04-20
申请号：US09823540
申请日：2001-03-30
申请人： Lam S. Dong
发明人： Lam S. Dong
IPC分类号： G06F1300
CPC分类号： G06F13/1684 , G06F13/1647 , G06F13/409
摘要： A multi-bank memory subsystem employing multiple memory modules. A memory subsystem includes a memory controller coupled to a memory bus. The memory bus includes a plurality of data paths each corresponding to a separate grouping of data lines. The memory bus is coupled to a first plurality of memory modules corresponding to a first memory bank. The first memory bank corresponding to a first range of addresses. The memory bus is also coupled to a second plurality of memory modules corresponding to a second memory bank. The second memory bank corresponding to a second range of addresses. A separate memory module of each of the first and the second memory banks is coupled to each data path of the memory bus. Memory modules that are coupled to the same data path are located adjacent to one another without any intervening memory modules coupled to other data paths.
摘要翻译：采用多个存储器模块的多存储存储器子系统。存储器子系统包括耦合到存储器总线的存储器控制器。存储器总线包括多个数据路径，每个对应于数据线的单独分组。存储器总线耦合到对应于第一存储体的第一多个存储器模块。第一存储体对应于第一范围的地址。存储器总线还耦合到对应于第二存储体的第二多个存储器模块。第二存储体对应于第二范围的地址。第一和第二存储器组中的每一个的单独存储器模块耦合到存储器总线的每个数据路径。耦合到相同数据路径的存储器模块彼此相邻定位，而没有任何中间存储器模块耦合到其他数据路径。

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