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1. 发明授权

US6145063A Memory system and information processing system 失效
标题翻译：内存系统和信息处理系统
公开(公告)号：US6145063A
公开(公告)日：2000-11-07
申请号：US120730
申请日：1998-07-23
申请人： Kiyoji Ueno , Nobuyuki Ikumi
发明人： Kiyoji Ueno , Nobuyuki Ikumi
IPC分类号： G11C11/407 , G06F12/02 , G06F12/06 , G06F13/16 , G11C11/401 , G06F12/00
CPC分类号： G06F12/0215 , G06F12/0607 , G06F13/1631 , G06F13/1647 , Y02B60/1225 , Y02B60/1228
摘要： In a memory composed of a plurality of banks, even if succeeding access is performed to the same bank as that being currently accessed, the succeeding access can be controlled according to the destination which is currently accessed and its accessed state. In addition, if particular relationships exist between a precedingly accessed destination and the succeedingly accessed destination, a corresponding main word line out of main word lines which correspond to respective rows of respective banks can be still held in its selected state even after the preceding access has been terminated.
摘要翻译：在由多个存储体组成的存储器中，即使对与当前访问的同一个存储体进行成功的访问，也可以根据当前访问的目的地及其访问状态来控制后续访问。此外，如果在先前访问的目的地和随后访问的目的地之间存在特定的关系，则即使在先前访问之后，对应于相应行的各行的主字线中的对应主字线仍然可以保持在其选择的状态已被终止。

2. 发明授权

US4860242A Precharge-type carry chained adder circuit 失效
标题翻译：预充电式进位链式加法器电路
公开(公告)号：US4860242A
公开(公告)日：1989-08-22
申请号：US294940
申请日：1989-01-05
申请人： Nobuyuki Ikumi
发明人： Nobuyuki Ikumi
IPC分类号： G06F7/50 , G06F7/506 , G06F7/508
CPC分类号： G06F7/506 , G06F2207/3872
摘要： In a prehcarge-type carry chained adder circuit, stages as represented by adders are grouped into a plurality of blocks each consisting of a plurality of stages. When the propagating functions of the stages of each block are active, a carry signal reproduced from the preceding block is transferred to the succeeding blocks through a bypass circuit.
摘要翻译：在前置放大型进位链式加法器电路中，由加法器表示的级被分组成多个块，每个块由多个级组成。当每个块的级的传播功能有效时，从前一块再现的进位信号通过旁路电路传送到后续块。

3. 发明授权

US06543033B2 Circuit design apparatus, circuit design method, circuit design program and semiconductor integrated circuit fabrication method 失效
标题翻译：电路设计装置，电路设计方法，电路设计程序和半导体集成电路制造方法
公开(公告)号：US06543033B2
公开(公告)日：2003-04-01
申请号：US09816244
申请日：2001-03-26
申请人： Itaru Yamazaki , Nobuyuki Ikumi
发明人： Itaru Yamazaki , Nobuyuki Ikumi
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： In a circuit design method, an arrangement/wiring section (112) determines an arrangement and wiring of logical blocks (40a, 40b, 40c, 40d) so that delay limitation information about input signals supplied to the logical blocks (40a, 40b, 40c, 40d) and limitation conditions about a difference of delay times among a pre-charge control signal (ck0, ck1, ck2) supplied to the corresponding logical lock (40a, 40b, 40c, 40d) and the input signals are satisfied.
摘要翻译：在电路设计方法中，布置/布线部分（112）确定逻辑块（40a，40b，40c，40d）的布置和布线，使得关于提供给逻辑块（40a，40b，40c）的输入信号的延迟限制信息，40d）和关于提供给相应逻辑锁（40a，40b，40c，40d）的预充电控制信号（ck0，ck1，ck2）与输入信号之间的延迟时间差的限制条件被满足。

4. 发明授权

US4825401A Functional dividable multiplier array circuit for multiplication of full words or simultaneous multiplication of two half words 失效
标题翻译：功能可分频乘法器阵列电路，用于乘以全字或同时乘以两个半字
公开(公告)号：US4825401A
公开(公告)日：1989-04-25
申请号：US25201
申请日：1987-03-12
申请人： Nobuyuki Ikumi
发明人： Nobuyuki Ikumi
IPC分类号： G06F7/533 , G06F7/507 , G06F7/508 , G06F7/52 , G06F7/53
CPC分类号： G06F7/5338 , G06F2207/3828
摘要： A multiplier array circuit including decoders for decoding a multiplier on the basis of Booth's algorithm; cell array blocks for receiving the selection signals from the decoders and a multiplicand and performing the multiplication of the multiplicand and the multiplier on the basis of Booth's algorithm; and an adder for obtaining the final products on the basis of the outputs from the cell array blocks. In order to enable the functionally divisional operation, the cell array blocks includes complex cells which operate as the basic cells in the non-division mode and which operate as the code cells in the division mode. Further, the cell array blocks include selectors to supply an inactive value to the cells to perform the multiplication of the upper bits of the multiplicand and the lower bits of the multiplier and to the cells to perform the multiplication of the lower bits of the multiplicand and the upper bits of the multiplier in such a manner that the cell array blocks can supply the multiplicand and its inverted data to the cells constituting the cell array blocks in the non-division mode and can simultaneously execute two series of multiplications in the division mode.

5. 发明授权

US5005117A Three-dimensional computer graphics apparatus with two-port memory for storing depth information 失效
标题翻译：具有双端口存储器的三维计算机图形设备用于存储深度信息
公开(公告)号：US5005117A
公开(公告)日：1991-04-02
申请号：US251164
申请日：1988-09-29
申请人： Nobuyuki Ikumi
发明人： Nobuyuki Ikumi
IPC分类号： G06T15/40 , H04N13/00
CPC分类号： H04N13/0055 , G06T15/405 , H04N13/0051 , H04N19/597 , H04N2013/0081
摘要： Depth information is stored in a 2-port memory having a random port and a serial port. The depth information is read out from the serial port of the 2-port memory and is supplied to an integrated circuit. The integrated circuit performs pipeline processing by using the depth information read out from the 2-port memory. If write-in is necessary as a result of the pipeline processing, the processed depth information is supplied to the random port of the 2-port memory, and the depth information is stored once again in the 2-port memory.

6. 发明授权

US5943038A Liquid crystal display panel 失效
标题翻译：液晶显示面板
公开(公告)号：US5943038A
公开(公告)日：1999-08-24
申请号：US760705
申请日：1996-12-05
申请人： Nobuyuki Ikumi
发明人： Nobuyuki Ikumi
IPC分类号： G02F1/133 , G06T15/40 , G09G3/20 , G09G3/36 , G09G5/36
CPC分类号： G09G3/3659 , G09G2300/0842 , G09G3/2074
摘要： An LCD panel capable of displaying three-dimensional images has, for each pixel, a transparent part and an opaque active element region. The active element region includes an input unit for receiving depth data including at least a depth and supplying the depth data to the pixel, a holder (Zc) for holding depth data, and a determination unit for determining which one of the depth data provided by the input unit and stored in the holder (Zc) is shallower, i.e., closer to a display screen than the other. The determined depth is used to display an object on the pixel.
摘要翻译：对于每个像素，能够显示三维图像的LCD面板具有透明部分和不透明有源元件区域。有源元件区域包括用于接收深度数据的输入单元，该深度数据至少包括深度并向像素提供深度数据，用于保持深度数据的保持器（Zc），以及确定单元，用于确定由存储在保持器（Zc）中的输入单元较浅，即比另一个更接近显示屏。确定的深度用于在像素上显示对象。

7. 发明授权

US5228135A Multiport cache memory control unit including a tag memory having plural address ports and a snoop address part 失效
标题翻译：多端口高速缓冲存储器控制单元包括具有多个地址端口的标签存储器和窥探地址部分
公开(公告)号：US5228135A
公开(公告)日：1993-07-13
申请号：US645642
申请日：1991-01-25
申请人： Nobuyuki Ikumi
发明人： Nobuyuki Ikumi
IPC分类号： G06F12/08
CPC分类号： G06F12/0853 , G06F12/0831
摘要： A multiport cache memory control unit includes a central processing unit having N arithmetic units for executing arithmetic processing, a tag memory having N address ports for storing addresses, a multiport cache memory having N data ports for storing pieces of data at addresses which agree with the addresses stored in the tag memory, and a snoop address port through which a snoop operation is executed to detect an address signal. Arithmetic processing is executed in each of the arithmetic units by reading a piece of data from the cache memory after providing an address signal to the tag memory to check whether or not the data is stored in the cache memory. In cases where a cache miss occurs, a piece of data stored in a main memory unit is fetched through the snoop address port without halting the arithmetic processing. In cases where a snoop hit occurs, an address signal provided from another control unit is transmitted to the tag memory through the snoop address port without halting the arithmetic processing.
摘要翻译：多端口高速缓冲存储器控制单元包括具有用于执行算术处理的N个算术单元的中央处理单元，具有用于存储地址的N个地址端口的标签存储器，具有N个数据端口的多端口高速缓冲存储器，用于存储与存储在标签存储器中的地址，以及通过其进行窥探操作以检测地址信号的窥探地址端口。通过在向标签存储器提供地址信号之后从高速缓冲存储器读取一条数据，以检查数据是否存储在高速缓冲存储器中，在每个运算单元中执行算术处理。在出现高速缓存未命中的情况下，通过侦听地址端口取出存储在主存储单元中的一条数据，而不会停止运算处理。在发生窥探命中的情况下，从另一个控制单元提供的地址信号通过窥探地址端口发送到标签存储器，而不会停止运算处理。

8. 发明授权

US5163127A Three dimensional graphic processing apparatus 失效
标题翻译：三维图形处理装置
公开(公告)号：US5163127A
公开(公告)日：1992-11-10
申请号：US687772
申请日：1991-04-19
申请人： Nobuyuki Ikumi , Mitsuo Saito , Takeshi Aikawa , Masahide Ohhashi
发明人： Nobuyuki Ikumi , Mitsuo Saito , Takeshi Aikawa , Masahide Ohhashi
IPC分类号： G06T15/40 , G06T15/80
CPC分类号： G06T15/87
摘要： A three-dimensional graphic processing apparatus includes n arithmetic ICs (Integrated Circuits) for performing linear interpolation calculations for each scan line of a triangle polygon to obtain intensity values and depth coordinate values of pixels, and two types of n memories for storing the calculation results. The n arithmetic ICs parallelly execute linear interpolation calculations of n different pixels successive on a single scan line of a single triangle polygon in one processing cycle. Each arithmetic IC calculates for each of every n pixels in one processing cycle, and a corresponding one of the memories stores the calculation result.
摘要翻译：三维图形处理装置包括用于对三角形多边形的每条扫描线进行线性插值计算的n个运算IC（集成电路），以获得像素的强度值和深度坐标值，以及用于存储计算结果的两种类型的n个存储器。在一个处理周期中，n个运算IC并行地执行在单个三角形多边形的单个扫描线上连续的n个不同像素的线性插值计算。每个算术IC在一个处理周期中为每n个像素计算每个运算IC，并且相应的一个存储器存储计算结果。

9. 发明授权

US4896294A Semiconductor memory device with row and column word lines and row and column bit lines 失效
标题翻译：具有行和列字线以及行和列位线的半导体存储器件
公开(公告)号：US4896294A
公开(公告)日：1990-01-23
申请号：US261866
申请日：1988-10-25
申请人： Mitsuru Shimizu , Nobuyuki Ikumi
发明人： Mitsuru Shimizu , Nobuyuki Ikumi
IPC分类号： G11C11/401 , G11C8/12 , G11C11/404 , G11C11/408
CPC分类号： G11C11/404 , G11C11/408 , G11C8/12
摘要： A memory cell contains a first MOS transistor, a second MOS transistor, and a capacitor, which are connected at the first ends to one another. A word line for a first cell series, is connected to the gates of first MOS transistors in the memory cells arrayed in a row. A word line for a second cell series, is connected to the gates of second MOS transistors arrayed in a column. A bit line for the first cell series, is connected to the second ends of the first MOS transistors in the row. A bit line for the second cell series, is connected to the second ends of the second MOS transistors in the column. A selection circuit selects the first cell series or the second cell series, according to an external input signal for cell series selection. According to the semiconductor memory deivce, one of the first and second cell array series of the memory cell array can be accessed according to a logic level of the array series select signal.

10. 发明授权

US5630084A System for converting data in little endian to big endian and vice versa by reversing two bits of address referencing one word of four words 失效
标题翻译：用于通过将参考四个字中的一个字的两位地址反转来将小端序数据转换为大字节的系统，反之亦然
公开(公告)号：US5630084A
公开(公告)日：1997-05-13
申请号：US872359
申请日：1992-04-23
申请人： Nobuyuki Ikumi
发明人： Nobuyuki Ikumi
IPC分类号： G06F7/76 , G06F9/34 , G06F12/04 , G06F9/30
CPC分类号： G06F7/768 , G06F12/04 , G06F9/34
摘要： A data processing device including: data processor handling at one time a plurality of data such as instructions each consisting of one word; a plurality of input ports for inputting a plurality of data; a memory for storing temporarily the data inputted through the input pins, each of whose elements consisting of one byte; and exclusive OR gates for designating each of the elements of the memory. Each portion of a memory element is referenced by a byte address each consisting two bits wherein when the information device can handle data formed in a Little-endian-type, in which the address are increased in sequence from the byte on the Least significant Bit (LSB), and the data is formed in a big-endian-type, in which the byte address are increased in sequence from the byte on the Most Significant Bit (MSB), the exclusive OR gates reverse some of the bits of each byte address.
摘要翻译：一种数据处理装置，包括：数据处理器一次处理多个数据，例如由一个字组成的指令; 用于输入多个数据的多个输入端口; 用于暂时存储通过输入引脚输入的数据的存储器，其每个元素由一个字节组成; 以及用于指定存储器的每个元件的异或门。存储器元件的每个部分由每个包括两个位的字节地址引用，其中当信息设备可以处理以小端序型形成的数据时，其中地址从最低有效位上的字节顺序增加（ LSB），并且数据形成为大字节型，其中字节地址从最高有效位（MSB）上的字节顺序增加，异或门反转每个字节地址的某些位。

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