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41. 发明申请

US20070255442A1 Process fault analyzer and method and storage medium 审中-公开
标题翻译：过程故障分析仪及方法及存储介质
公开(公告)号：US20070255442A1
公开(公告)日：2007-11-01
申请号：US11717781
申请日：2007-03-14
申请人： Toshikazu Nakamura , Shigeru Obayashi , Kenichiro Hagiwara , Yoshikazu Aikawa
发明人： Toshikazu Nakamura , Shigeru Obayashi , Kenichiro Hagiwara , Yoshikazu Aikawa
IPC分类号： G06F19/00
CPC分类号： G05B23/024
摘要： The process fault analyzer includes a process data editing part for extracting a process characteristic quantity from process data in a time series stored in a process data storing part, a fault analysis rule data storing part for storing a fault analysis rule for performing fault detection on a product manufactured in a manufacturing system and on manufacturing equipment, based on the process characteristic quantity, and a fault determining part for determining existence/absence of a fault in a product and in manufacturing equipment based on the process characteristic quantity. A partial least square regression (PLS) model is used as an estimation model used for the fault analysis rule. Also, Q statistics and T2 statistics are used, and the fault determining part determines a fault in manufacturing equipment when values of the statistics are the same as set value or more.
摘要翻译：过程故障分析器包括：处理数据编辑部分，用于从存储在过程数据存储部分中的时间序列中的过程数据中提取处理特征量;故障分析规则数据存储部分，用于存储用于对故障检测执行故障检测的故障分析规则; 基于过程特征量在制造系统和制造设备中制造的产品，以及基于处理特征量的用于确定产品和制造设备中的故障的存在/不存在的故障确定部。使用偏最小二乘回归（PLS）模型作为用于故障分析规则的估计模型。此外，使用Q统计和T 2等级统计，并且当统计量的值与设定值相同时，故障确定部分确定制造设备中的故障。

42. 发明申请

US20070192064A1 Process fault analyzer and system, program and method thereof 审中-公开
标题翻译：过程故障分析仪及其系统，程序及方法
公开(公告)号：US20070192064A1
公开(公告)日：2007-08-16
申请号：US11705598
申请日：2007-02-13
申请人： Toshikazu Nakamura , Shigeru Obayashi , Kenichiro Hagiwara , Yoshikazu Aikawa
发明人： Toshikazu Nakamura , Shigeru Obayashi , Kenichiro Hagiwara , Yoshikazu Aikawa
IPC分类号： G06F19/00
CPC分类号： G06Q10/06
摘要： A process fault analyzer, capable of analyzing fault caused due to a process performed by a plurality of process equipments, is provided. The analyzer includes: a plurality of process data storing units which store process data of the respective process equipments; a process data editing unit which calculates process characteristic quantity from various kinds of process data stored on the process data storing units; a plurality of process characteristic quantity data storing units which store process characteristic quantity of the respective process equipments calculated by the process data editing unit; a process characteristic quantity integration unit which accesses the process characteristic quantity data storing units, extracts process characteristic quantity of the same wafer, and integrates them; and a fault determination unit which determines presence or absence of fault according to the integrated process characteristic quantity data integrated by the process characteristic quantity integration unit.
摘要翻译：提供一种能够分析由多个处理设备进行的处理引起的故障的过程故障分析器。分析器包括：多个处理数据存储单元，存储各个处理设备的处理数据; 处理数据编辑单元，其从存储在处理数据存储单元上的各种处理数据计算处理特征量; 多个处理特征量数据存储单元，其存储由处理数据编辑单元计算出的各个处理设备的处理特征量; 访问处理特征量数据存储单元的处理特征量整合单元，提取同一晶片的处理特征量，并对其进行积分; 以及故障判定单元，其根据由所述处理特征量积分单元积分的积分处理特征量数据来判定是否存在故障。

43. 发明授权

US07243274B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07243274B2
公开(公告)日：2007-07-10
申请号：US11206170
申请日：2005-08-18
申请人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
发明人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/36
摘要： An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.
摘要翻译：外部终端接收外部信号以访问第一和第二存储器芯片。当第一和第二存储器芯片正常工作时，测试启动终端接收到测试启动信号，当第一或第二存储器芯片被测试和非激活时激活。访问信号发生器将外部信号转换为第一存储器芯片的存储器访问信号。第一选择器在激活测试启动信号期间选择作为测试信号的外部信号，在测试启动信号失效期间选择存储器访问信号。也就是说，在测试模式期间，可以从外部直接访问第一存储器芯片。因此，在半导体器件的组装之后，用于单独测试第一存储器芯片的测试程序可以作为测试程序转移。

44. 发明申请

US20070021335A1 Agent for improving mental disorders 审中-公开
标题翻译：改善精神障碍的药剂
公开(公告)号：US20070021335A1
公开(公告)日：2007-01-25
申请号：US10575712
申请日：2004-08-13
申请人： Satoshi Takeo , Keiko Takagi , Norio Takagi , Toshikazu Nakamura
发明人： Satoshi Takeo , Keiko Takagi , Norio Takagi , Toshikazu Nakamura
IPC分类号： A61K38/18
CPC分类号： A61K38/1833
摘要： The present invention provides an agent for improving mental disorders due to cerebral dysfunction and an agent for inhibiting vascular hyperpermeability each containing a hepatocyte growth factor. The agent for improving mental disorders according to the present invention is useful in improving mental disorders, particularly decline in learning and memory function, due to cerebral dysfunction occurred in blood circulation disorders in the brain (for example, cerebral infarction, cerebral hemorrhage, lacunar stroke, Biswanger's disease, cerebral thrombosis, subarachnoid hemorrhage, cerebrovascular moyamoya disease, carotid cerebral arterial fibrous muscular plasia, cerebral arterial sclerosis, internal carotid artery occlusion, hypertensive encephalopathy, cerebral edema, etc.) and neurodegenerative disorders (for example, multiple sclerosis, Parkinson's disease, Parkinson'syndrome, Huntington's chorea, cerebrovascular dementia and Alzheimer dementia), epilepsy, head injury, etc. The agent for inhibiting vascular hyperpermeability according to the present invention is efficacious to blood hyperpermeability in the brain due to blood circulation disorders in the brain (for example, cerebral infarction, cerebral hemorrhage, lacunar stroke, Biswanger's disease, cerebral thrombosis, subarachnoid hemorrhage, cerebrovascular moyamoya disease, carotid cerebral arterial fibrous muscular plasia, cerebral arterial sclerosis, internal carotid artery occlusion, hypertensive encephalopathy, cerebral edema, etc.), blood leakage, edema, subcutaneous hemorrhage and bleeding tendency due to vascular hyperpermeability in various tissues (including internal organs).
摘要翻译：本发明提供一种用于改善由于脑功能障碍引起的精神障碍的药剂和每种含有肝细胞生长因子的抑制血管高渗透性的药剂。根据本发明的用于改善精神障碍的药剂可用于改善精神障碍，特别是由于脑中血液循环障碍中发生的脑功能障碍（例如脑梗塞，脑出血，腔隙性中风）引起的学习和记忆功能的下降，Biswanger氏病，脑血栓形成，蛛网膜下腔出血，脑血管性moyamoya病，颈动脉大脑动脉纤维性肌浆膜炎，脑动脉硬化，颈内动脉闭塞，高血压性脑病，脑水肿等）和神经退行性疾病（例如多发性硬化症，帕金森病疾病，帕金森综合症，亨廷顿氏舞蹈病，脑血管性痴呆和阿尔茨海默痴呆），癫痫，头部损伤等。根据本发明的用于抑制血管高渗透性的药剂由于脑中的血液循环障碍而对脑中的血液渗透性过高是有效的（例如，脑梗塞，脑出血，腔隙性脑卒中，Biswanger氏病，脑血栓形成，蛛网膜下腔出血，脑血管性moyamoya病，颈动脉脑动脉纤维性肌浆膜炎，脑动脉硬化，颈内动脉闭塞，高血压性脑病，脑水肿等），血液渗漏，水肿，皮下出血和出血倾向，由于各种组织（包括内脏器官）的血管渗透性过高。

45. 发明申请

US20050233299A1 Method for preserving organs for transplantation with a HGF-containing solution 审中-公开
标题翻译：用含HGF溶液保存移植器官的方法
公开(公告)号：US20050233299A1
公开(公告)日：2005-10-20
申请号：US10967247
申请日：2004-10-19
申请人： Yoshiki Sawa , Hikaru Matsuda , Toshikazu Nakamura , Shinya Mizuno
发明人： Yoshiki Sawa , Hikaru Matsuda , Toshikazu Nakamura , Shinya Mizuno
IPC分类号： A01N1/02
CPC分类号： A01N1/02 , A01N1/0226
摘要： A method of preserving a harvested organ, a harvested organ tissue or a part thereof for a long time, which comprises perfusing and/or immersing the harvested organ with a solution containing HGF having a temperature of 0 to 6° C., and which method is capable of maintaining harvested organs for transplantation in a high physiological state and preventing ischemia/reperfusion injury of the organs transplanted.
摘要翻译：一种长期保存收获的器官，收获的器官组织或其部分的方法，其包括用含有0至6℃温度的HGF的溶液灌注和/或浸没收获的器官，以及哪种方法能够在高生理状态下维持收集的器官移植，并预防移植器官的缺血/再灌注损伤。

46. 发明申请

US20050133953A1 Method for producing of cellulose ester film 有权
标题翻译：纤维素酯薄膜的制造方法
公开(公告)号：US20050133953A1
公开(公告)日：2005-06-23
申请号：US11061545
申请日：2005-02-18
申请人： Hidekazu Yamazaki , Toshikazu Nakamura , Hiroshi Miyachi
发明人： Hidekazu Yamazaki , Toshikazu Nakamura , Hiroshi Miyachi
IPC分类号： B29C41/28 , B29C41/32 , B29D7/01 , B29C39/14
CPC分类号： B29D7/01 , B29C41/28 , B29C41/32 , B29K2001/00 , B29K2001/12 , B29L2009/00
摘要： In order to produce a cellulose ester film constructed of a front layer, an intermittent layer and a rear layer, a dope solution is doped on a supporter. In at least one of the front layer and the rear layer, a mass ratio of a cotton linter to a wood pulp (cotton linter/wood pulp) is between 5/95 and 0/100, and a solvent of the dope contains more than 15 wt. % alcohols and hydrocarbons whose carbon number each is 1-10. Further, a ratio of a solid content density of a solution for forming the front layer and the rear layer to a solid density of a solution for forming the intermittent layer is less than 0.9 wt. %, and a total thickness of the solutions for front and rear layers is more than 5% of the dope ribbon.
摘要翻译：为了制造由前层，间歇层和后层构成的纤维素酯膜，在支持体上掺杂了掺杂溶液。在前层和后层中的至少一个中，棉绒与木浆（棉绒/木浆）的质量比在5/95至0/100之间，并且涂料的溶剂含有多于 15重量％碳数为1-10的醇和碳氢化合物。此外，用于形成前层和后层的溶液的固体成分密度与用于形成间歇层的溶液的固体密度的比例小于0.9重量％。％，并且前层和后层的溶液的总厚度大于涂料带的5％。

47. 发明申请

US20050052935A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050052935A1
公开(公告)日：2005-03-10
申请号：US10968072
申请日：2004-10-20
申请人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto
发明人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto
IPC分类号： G11C11/4097 , G11C8/00
CPC分类号： G11C11/4097
摘要： Second memory cells of a second memory block each have an area 2a times (a is a positive integer) that of each first memory cell of a first memory block. Sizing the first and second memory cells in a predetermined ratio can make easily identical the dimensions of the first memory block and the second memory block. Consequently, it is possible to easily align peripheral circuits to lie around the plurality of first and second memory blocks, such as decoders. This also facilitates the wiring of signal lines to be connected to the peripheral circuits. This makes it possible to improve the layout design efficiency for a semiconductor integrated circuit. Thus, a plurality of types of memory blocks can be formed on a semiconductor integrated circuit efficiently. The semiconductor integrated circuit can be prevented from increasing in chip size depending on the layout design, owing to its simplified layout.
摘要翻译：第二存储器块的第二存储器单元各自具有第一存储器块的每个第一存储器单元的区域2。以预定比例对第一和第二存储器单元进行尺寸可以使得第一存储块和第二存储块的尺寸容易相同。因此，可以容易地将外围电路对准在诸如解码器之类的多个第一和第二存储器块周围。这也有助于连接到外围电路的信号线的布线。这使得可以提高半导体集成电路的布局设计效率。因此，可以有效地在半导体集成电路上形成多种类型的存储块。由于布局简单，可以防止半导体集成电路因布局设计而增加芯片尺寸。

48. 发明授权

US06628564B1 Semiconductor memory device capable of driving non-selected word lines to first and second potentials 有权
标题翻译：能够将未选择的字线驱动到第一和第二电位的半导体存储器件
公开(公告)号：US06628564B1
公开(公告)日：2003-09-30
申请号：US09339855
申请日：1999-06-25
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C808
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.
摘要翻译：半导体器件包括字线驱动电路，通过驱动连接到存储单元的字线并在字线的复位操作时切换字线驱动电路的复位电平来重置字线。此外，半导体器件包括通过布置多个存储单元形成的存储单元阵列和用于选择第一电位或第二电位的复位电平开关电路，并将第一电位或第二电位提供给字线驱动电路。

49. 发明授权

US06605963B2 Semiconductor integrated circuit and method of switching source potential of transistor in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中半导体集成电路和晶体管的源极电位切换方法
公开(公告)号：US06605963B2
公开(公告)日：2003-08-12
申请号：US09412590
申请日：1999-10-05
申请人： Ayako Kitamoto , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Hideki Kanou , Kuninori Kawabata , Masatomo Hasegawa , Toru Koga , Yuki Ishii
发明人： Ayako Kitamoto , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Hideki Kanou , Kuninori Kawabata , Masatomo Hasegawa , Toru Koga , Yuki Ishii
IPC分类号： H03K19185
CPC分类号： H03K19/0013 , H03K3/356113 , H03K17/102 , H03K19/00361 , H03K2217/0036
摘要： A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.
摘要翻译：公开了一种半导体集成电路，其包括具有预定功能的电路单元，例如通过多个晶体管的组合的电平移位器电路或驱动晶体管电路。在电路单元的多个晶体管中，改变了在电路单元的待机期间适于关断的至少一个晶体管的源极电位。优选地，半导体集成电路被配置为减少在电路单元的待机时段期间流过至少一个晶体管的源极和漏极之间的亚阈值电流，其在基于以使得在晶体管的栅极和源极之间施加预定的偏置电压的方式使电路单元的待机时段。还公开了一种在具有上述结构的半导体集成电路中切换至少一个晶体管的源极电位的方法。

50. 发明授权

US06377101B1 Variable delay circuit and semiconductor integrated circuit device 有权
标题翻译：可变延迟电路和半导体集成电路器件
公开(公告)号：US06377101B1
公开(公告)日：2002-04-23
申请号：US09510299
申请日：2000-02-22
申请人： Satoshi Eto , Masao Taguchi , Masato Matsumiya , Toshikazu Nakamura , Masato Takita , Mitsuhiro Higashiho , Toru Koga , Hideki Kano , Ayako Kitamoto , Kuninori Kawabata , Koichi Nishimura , Yoshinori Okajima
发明人： Satoshi Eto , Masao Taguchi , Masato Matsumiya , Toshikazu Nakamura , Masato Takita , Mitsuhiro Higashiho , Toru Koga , Hideki Kano , Ayako Kitamoto , Kuninori Kawabata , Koichi Nishimura , Yoshinori Okajima
IPC分类号： H03H1126
CPC分类号： H03L7/0805 , G06F1/10 , H03K5/131 , H03K5/133 , H03L7/07 , H03L7/0814 , H03L7/0818 , H03L7/087 , H04L7/033
摘要： A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.
摘要翻译：可变延迟电路包括具有第一延迟量的第一栅极和具有大于第一延迟量的第二延迟量的第二栅极。第一延迟量和第二延迟时间之间的差小于第一延迟量。

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