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41. 发明授权

US6091863A Image processor and data processing system using the same processor 失效
标题翻译：图像处理器和数据处理系统使用相同的处理器
公开(公告)号：US6091863A
公开(公告)日：2000-07-18
申请号：US523509
申请日：1995-09-01
申请人： Keisuke Nakashima , Jun Satoh , Kazushige Yamagishi , Takashi Miyamoto , Kenichiro Omura , Koyo Katsura , Mitsuru Watabe
发明人： Keisuke Nakashima , Jun Satoh , Kazushige Yamagishi , Takashi Miyamoto , Kenichiro Omura , Koyo Katsura , Mitsuru Watabe
IPC分类号： G09G5/00 , G06F12/00 , G06T1/20 , G06T11/00 , G06T15/04 , G06K9/36 , G06F15/00 , G06K9/54
CPC分类号： G06T1/20
摘要： An image processor which is connected to a system bus that connects a processor for forming graphic command related to image processing to a main memory that holds command and original image data, and draws image on the frame buffer based upon said graphic command from said processor, wherein said graphic processor has a data bus change-over unit which connects said system bus to a first data bus that is connected to a graphic data memory holding said graphic command and said original image data, or connects said first data bus to a frame buffer which holds the data to be displayed. The image processor realizes a high-speed processing at a reduced cost by using a graphic memory bus coupled to a graphic processor.
摘要翻译：一种图像处理器，其连接到系统总线，该系统总线将用于形成与图像处理有关的图形命令的处理器连接到保存命令和原始图像数据的主存储器，并且基于来自所述处理器的所述图形命令在所述帧缓冲器上绘制图像，其中所述图形处理器具有数据总线转换单元，其将所述系统总线连接到连接到保存所述图形命令和所述原始图像数据的图形数据存储器的第一数据总线，或将所述第一数据总线连接到帧缓冲器它保存要显示的数据。图像处理器通过使用耦合到图形处理器的图形存储器总线以低成本实现高速处理。

42. 发明授权

US6091660A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US6091660A
公开(公告)日：2000-07-18
申请号：US376468
申请日：1999-08-18
申请人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
发明人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
IPC分类号： G11C11/401 , G11C8/00 , G11C8/12 , G11C11/407
CPC分类号： G11C8/12
摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
摘要翻译：安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。分别提供用于分别执行+1或-1算术运算的算术电路，以便对应于相应的存储器垫并且以级联形式电连接。初始级算术电路的输入端被提供地址设定固定地址信号。提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。基于所得到的一致信号来选择相应的存储器垫。

43. 发明授权

US5713011A Synchronized data processing system and image processing system 失效
公开(公告)号：US5713011A
公开(公告)日：1998-01-27
申请号：US317130
申请日：1994-10-03
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F3/153 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/12 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/00 , G06F13/14 , G06F13/16 , G06F15/00 , G06F15/76 , G06T1/00 , G06T1/20 , G06T1/60 , G09G5/36 , G09G5/393 , G11C5/00 , G11C11/401 , G11C11/407
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G09G5/399
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

44. 外观设计

USD338661S Streaming cassette tape drive 失效
公开(公告)号：USD338661S
公开(公告)日：1993-08-24
申请号：US736758
申请日：1991-07-26
申请人： Takashi Miyamoto
设计人： Takashi Miyamoto

45. 外观设计

USD331926S Magnetic tape cassette 失效
公开(公告)号：USD331926S
公开(公告)日：1992-12-22
申请号：US510900
申请日：1990-04-18
申请人： Kazuaki Urano , Yoshimi Maehara , Hiroshi Ohkubo , Takashi Miyamoto
设计人： Kazuaki Urano , Yoshimi Maehara , Hiroshi Ohkubo , Takashi Miyamoto

46. 发明授权

US09006934B2 Power feeding apparatus, power receiving apparatus, wireless power feeding system and method for wireless transfer of power 有权
标题翻译：供电装置，电力接收装置，无线供电系统及电力无线传输方法
公开(公告)号：US09006934B2
公开(公告)日：2015-04-14
申请号：US13080375
申请日：2011-04-05
申请人： Osamu Kozakai , Takashi Miyamoto , Yuji Murayama
发明人： Osamu Kozakai , Takashi Miyamoto , Yuji Murayama
IPC分类号： H01F27/42 , H01F37/00 , H01F38/00 , H03F1/56
CPC分类号： H03F1/565 , H02J50/20 , Y10T307/469 , Y10T307/707 , Y10T307/718
摘要： A power feeding apparatus, power receiving apparatus, wireless power feeding system, and method for wireless transfer of power are provided. The power feeding apparatus includes an impedance detector, a controller, a power transmitter, a variable matching circuit, and a signal transmitter. The controller is configured to provide first control information and second control information based on an impedance detected by the impedance detector. The power feeding apparatus' variable matching circuit is configured to change a variable diameter of a power feeding coil according to the first control information. The power receiving apparatus includes a power receiver, a signal receiver, and a variable matching circuit. The power receiving apparatus'variable matching circuit is configured to change a variable diameter of a power feeding coil according to the second control information provided by the power feeding apparatus.
摘要翻译：提供一种供电装置，电力接收装置，无线供电系统以及无线电力传输方法。馈电装置包括阻抗检测器，控制器，功率发射器，可变匹配电路和信号发射器。控制器被配置为基于由阻抗检测器检测到的阻抗来提供第一控制信息和第二控制信息。供电装置的可变匹配电路被配置为根据第一控制信息改变供电线圈的可变直径。电力接收装置包括电力接收器，信号接收器和可变匹配电路。电力接收装置的变形匹配电路被配置为根据由馈电装置提供的第二控制信息来改变供电线圈的可变直径。

47. 发明申请

US20130166163A1 DRIVE SYSTEM CONTROL DEVICE FOR WORKING VEHICLE 有权
标题翻译：用于工作车辆的驱动系统控制装置
公开(公告)号：US20130166163A1
公开(公告)日：2013-06-27
申请号：US13821420
申请日：2011-09-07
申请人： Takeshi Oouchida , Keiichirou Yuzaki , Takashi Miyamoto , Tadao Hirai
发明人： Takeshi Oouchida , Keiichirou Yuzaki , Takashi Miyamoto , Tadao Hirai
IPC分类号： B60W10/06 , B60W10/101
CPC分类号： B60W10/06 , B60W10/101 , B60W10/103 , B60W10/30 , B60Y2200/221 , B60Y2300/476 , F01N3/035 , F01N3/106 , F02D29/00 , F02D41/029 , F02D2041/026 , F16H2061/0018 , F16H2061/0232 , Y02A50/2322
摘要： In a working vehicle provided with an engine which is mounted to a travel machine body, a common rail type fuel injection device which injects fuel to the engine, a continuously variable transmission which shifts power from the engine, and the exhaust gas purification device which is arranged in an exhaust system of the engine, in the case that an engine operating point Q relating to a rotating speed N and a torque T of the engine is in a low-speed and low-torque side incapable of self-renewing the exhaust gas purification device, the engine operating point Q is changed to a high-speed and low-torque side capable of self-renewing the exhaust gas purification device, and a change gear ratio of the continuously variable transmission is changed and regulated in such a manner that a vehicle speed V of the travel machine body is not changed.
摘要翻译：在设置有安装在行进机体上的发动机的作业车辆中，向发动机喷射燃料的共轨式燃料喷射装置，将发动机的动力转向的无级变速器和作为发动机的动力的排气净化装置在发动机的排气系统中，在与发动机的转速N和转矩T有关的发动机工作点Q处于不能自动更新废气的低速低转矩侧的情况下，净化装置，将发动机工作点Q变更为能够自动更新废气净化装置的高速低扭矩侧，并且以无级变速器的变速比来改变和调节变速比，行驶机体的车速V不变化。

48. 发明授权

US08410367B2 Electric contact member 有权
标题翻译：电接触件
公开(公告)号：US08410367B2
公开(公告)日：2013-04-02
申请号：US12895050
申请日：2010-09-30
申请人： Takayuki Hirano , Akashi Yamaguchi , Takashi Miyamoto
发明人： Takayuki Hirano , Akashi Yamaguchi , Takashi Miyamoto
IPC分类号： H01B5/00
CPC分类号： H01B5/00 , G01R1/06738 , G01R1/06761 , H01R13/03
摘要： Provided is an electric contact member which reduces, to the utmost, peel-off of a carbon film that is caused at the time of use of the electric contact member having at least an edge to keep stable electric contact over a long period of time. Disclosed is an electric contact member which repeatedly contacts with a device under test at a tip part of the electric contact member in which the tip part has an edge, the electric contact member comprising: a base material; an underlying layer comprising Au, Au alloy, Pd or Pd alloy, which is formed on a surface of the base material of the tip part; an intermediate layer which is formed on a surface of the underlying layer; and a carbon film comprising at least one of a metal and a carbide thereof which is formed on a surface of the intermediate layer, wherein the intermediate layer has a lamination structure comprising: an inner layer comprising Ni or Ni alloy; and an outer layer comprising at least one of Cr, Cr alloy, W and W alloy.
摘要翻译：提供一种电接触构件，其最大限度地减少在使用具有至少边缘的电接触构件在长时间内保持稳定的电接触时引起的碳膜的剥离。公开了一种电接触构件，其在尖端部具有边缘的电接触构件的尖端部分处与被测试器件重复接触，该电接触构件包括：基底材料; 包含Au，Au合金，Pd或Pd合金的下层，其形成在尖端部分的基材的表面上; 形成在下层的表面上的中间层; 以及形成在所述中间层的表面上的金属和碳化物中的至少一种的碳膜，其中所述中间层具有层叠结构，所述层叠结构包括：包含Ni或Ni合金的内层; 以及包含Cr，Cr合金，W和W合金中的至少一种的外层。

49. 发明授权

US08402953B2 Engine 有权
标题翻译：发动机
公开(公告)号：US08402953B2
公开(公告)日：2013-03-26
申请号：US12743118
申请日：2008-11-11
申请人： Takao Kawabe , Takashi Miyamoto , Terumitsu Takahata , Tetsuo Sakaki , Isamu Kawashima
发明人： Takao Kawabe , Takashi Miyamoto , Terumitsu Takahata , Tetsuo Sakaki , Isamu Kawashima
IPC分类号： F02B33/00
CPC分类号： F02D41/0007 , F02B37/12 , F02B2039/168 , F02D41/221 , Y02T10/144
摘要： It is an object to provide an engine that makes it possible to constantly detect the number of rotations of a supercharger with a calculation load of an ECU reduced. An engine 1 is provided with an engine base 8 comprised of a plurality of cylinders and a turbocharger 7, a crank angle sensor 4, a turbo sensor 5 that detects rotations of the turbocharger 7 as pulses, an amplifier 11 that divides the pulses by an arbitrary division ratio and calculates the divided pulses, and an ECU 10 that judges a surge condition of the turbocharger 7, wherein the ECU 10 sets a predetermined position of a piston of each cylinder in a crank angle of the engine base 8 to count start timing of the divided pulses, outputs the divided pulses counted from the count start timing to the number of predetermined rotations as a first output, and judges that, if a difference between the first outputs at every cylinder is more than a predetermined value, the turbocharger 7 is in the surge condition.
摘要翻译：本发明的目的是提供一种发动机，其能够以减少的ECU的计算负荷来不断地检测增压器的转数。发动机1设置有由多个气缸构成的发动机基座8和涡轮增压器7，曲轴转角传感器4，涡轮增压器7的旋转作为脉冲的涡轮传感器5，将脉冲除以一个任意分频比，并计算分割脉冲，以及判断涡轮增压器7的喘振状态的ECU10，其中，ECU10将各气缸的活塞的规定位置设定在发动机基座8的曲轴角度，以计数开始时刻将从计数开始定时开始计数的分割脉冲输出为第一输出的规定转数，判断为每个气缸的第一输出之间的差大于预定值时，涡轮增压器7 处于喘振状态。

50. 发明授权

US08332683B2 Data processing system and image processing system 失效
标题翻译：数据处理系统和图像处理系统
公开(公告)号：US08332683B2
公开(公告)日：2012-12-11
申请号：US12731442
申请日：2010-03-25
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/04
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译：一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

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