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    • 10. 发明授权
    • Picture processing apparatus and picture processing method
    • 图像处理装置和图像处理方法
    • US06600492B1
    • 2003-07-29
    • US09292375
    • 1999-04-15
    • Tetsuya ShimomuraShigeru MatsuoKazuyoshi KogaKoyo KatsuraYasuhiro NakatsukaKazushige Yamagishi
    • Tetsuya ShimomuraShigeru MatsuoKazuyoshi KogaKoyo KatsuraYasuhiro NakatsukaKazushige Yamagishi
    • G06T1500
    • G06T1/60
    • In order to assure that a plurality of circuits such as a CPU I/F circuit, a rendering circuit, a video input circuit and a display circuit, which are each required to always complete a processing within a prescribed time, are each assured the ability to make as many accesses to a memory as required to complete the processing within the prescribed time, it is necessary to arbitrate a contention for an access to the memory through an internal bus among the circuits by employing a bus control circuit wherein priority levels assigned to the circuits to make an access to the internal bus are dynamically changed by comparing degrees of access urgency among the circuits. In this way, circuits that each have to always complete theirs processing within a prescribed time are assured the ability to make as many accesses to the memory as required to complete the processing within the prescribed time even if a plurality of such circuits do exist.
    • 为了确保在规定时间内需要总是完成处理的多个电路,例如CPU I / F电路,再现电路,视频输入电路和显示电路,都能确保能力 为了在规定的时间内对存储器进行尽可能多的访问以完成处理,有必要通过使用总线控制电路来通过内部总线来仲裁访问存储器的争用,其中优先级分配给 通过比较电路之间的访问紧急程度来动态地改变访问内部总线的电路。 以这种方式,每个必须总是在规定时间内完成它们的处理的电路确保了即使存在多个这样的电路,也可以在规定的时间内完成处理所需的存储器的访问的能力。