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1. 发明授权

US07557809B2 Memory access methods in a unified memory system 有权
标题翻译：内存访问方法在统一的内存系统中
公开(公告)号：US07557809B2
公开(公告)日：2009-07-07
申请号：US10983757
申请日：2004-11-09
申请人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
发明人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
IPC分类号： G06F13/14 , G09G5/39 , G06F15/167
CPC分类号： G09G5/39 , G09G2360/125
摘要： The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
摘要翻译：多媒体数据处理系统的基本部分包括CPU 1100，图像显示单元2100，统一存储器1200，系统总线1920和连接到系统总线的设备1300,1400和1500。在这种配置中，CPU形成在安装在包括指令处理单元1110和显示控制单元1140的单个硅晶片上的LSI上。主存储区域1210和显示区域1220存储在统一存储器内。与用于连接LSI和输入/输出设备的系统总线无关地提供用于连接对应的LSI和统一存储器的统一存储器端口1910。统一的存储器端口可以比系统总线更快地驱动。

2. 发明授权

US06839063B2 Memory access methods in a unified memory system 有权
标题翻译：内存访问方法在统一的内存系统中
公开(公告)号：US06839063B2
公开(公告)日：2005-01-04
申请号：US09791817
申请日：2001-02-26
申请人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
发明人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
IPC分类号： G06F13/16 , G06F3/153 , G06F12/00 , G06F12/04 , G09G5/39 , G06F13/372
CPC分类号： G09G5/39 , G09G2360/125
摘要： The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

3. 发明授权

US06745279B2 Memory controller 失效
标题翻译：内存控制器
公开(公告)号：US06745279B2
公开(公告)日：2004-06-01
申请号：US09962257
申请日：2001-09-26
申请人： Yuichiro Morita , Manabu Jyou , Yasuhiro Nakatsuka , Tetsuya Shimomura , Yutaka Okada , Kazushige Yamagishi
发明人： Yuichiro Morita , Manabu Jyou , Yasuhiro Nakatsuka , Tetsuya Shimomura , Yutaka Okada , Kazushige Yamagishi
IPC分类号： G06F1200
CPC分类号： G06F13/161
摘要： A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.
摘要翻译：公开了一种存储器控制器，其中在从设备接收到访问请求时，存储器控制器基于访问请求以预定的存储器周期来激活由第一存储体的行地址指定的页面。之后，在对第一个银行的页面的读取访问之前，接下来要访问的第二个银行被预充电。在通过读取操作访问第一存储体之后，由于通过图形处理从第一存储体到第二存储体的访问发生页面错误的情况下，存储器控制器立即激活第二存储体而不进行预充电。

4. 发明授权

US06587111B2 Graphic processor and data processing system 有权
公开(公告)号：US06587111B2
公开(公告)日：2003-07-01
申请号：US09983716
申请日：2001-10-25
申请人： Atsushi Nakamura , Yasuhiro Nakatsuka , Kazushige Yamagishi
发明人： Atsushi Nakamura , Yasuhiro Nakatsuka , Kazushige Yamagishi
IPC分类号： G06T100
CPC分类号： G06T15/005 , G09G5/363 , G09G5/393 , G09G5/399 , G09G2340/10 , H04N7/0132
摘要： A graphic processor including a rendering control circuit which carries out weighted averaging on pieces of pixel data of source image information arranged to form a pixel-data matrix corresponding to a pixel matrix with columns of the pixel-data matrix being oriented perpendicularly to a scanning direction in order to compute a weighted average of pieces of pixel data on rows of the pixel-data matrix adjacent to each other and on a column of the pixel-data matrix perpendicular to the scanning direction in so-called blend processing. The rendering control circuit reads out pieces of pixel data from the pixel-data matrix sequentially in a direction perpendicular to the scanning direction and computes a weighted average of the pieces of data. Image data subjected to blend processing is displayed by adopting an interlace scanning technique thereby eliminating undesired flicker.

5. 发明授权

US06288728B1 Data processing system and image processing system 有权
标题翻译：数据处理系统和图像处理系统
公开(公告)号：US06288728B1
公开(公告)日：2001-09-11
申请号：US09583721
申请日：2000-05-30
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1576
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译：一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

6. 发明授权

US6091863A Image processor and data processing system using the same processor 失效
标题翻译：图像处理器和数据处理系统使用相同的处理器
公开(公告)号：US6091863A
公开(公告)日：2000-07-18
申请号：US523509
申请日：1995-09-01
申请人： Keisuke Nakashima , Jun Satoh , Kazushige Yamagishi , Takashi Miyamoto , Kenichiro Omura , Koyo Katsura , Mitsuru Watabe
发明人： Keisuke Nakashima , Jun Satoh , Kazushige Yamagishi , Takashi Miyamoto , Kenichiro Omura , Koyo Katsura , Mitsuru Watabe
IPC分类号： G09G5/00 , G06F12/00 , G06T1/20 , G06T11/00 , G06T15/04 , G06K9/36 , G06F15/00 , G06K9/54
CPC分类号： G06T1/20
摘要： An image processor which is connected to a system bus that connects a processor for forming graphic command related to image processing to a main memory that holds command and original image data, and draws image on the frame buffer based upon said graphic command from said processor, wherein said graphic processor has a data bus change-over unit which connects said system bus to a first data bus that is connected to a graphic data memory holding said graphic command and said original image data, or connects said first data bus to a frame buffer which holds the data to be displayed. The image processor realizes a high-speed processing at a reduced cost by using a graphic memory bus coupled to a graphic processor.
摘要翻译：一种图像处理器，其连接到系统总线，该系统总线将用于形成与图像处理有关的图形命令的处理器连接到保存命令和原始图像数据的主存储器，并且基于来自所述处理器的所述图形命令在所述帧缓冲器上绘制图像，其中所述图形处理器具有数据总线转换单元，其将所述系统总线连接到连接到保存所述图形命令和所述原始图像数据的图形数据存储器的第一数据总线，或将所述第一数据总线连接到帧缓冲器它保存要显示的数据。图像处理器通过使用耦合到图形处理器的图形存储器总线以低成本实现高速处理。

7. 发明授权

US5713011A Synchronized data processing system and image processing system 失效
公开(公告)号：US5713011A
公开(公告)日：1998-01-27
申请号：US317130
申请日：1994-10-03
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F3/153 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/12 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/00 , G06F13/14 , G06F13/16 , G06F15/00 , G06F15/76 , G06T1/00 , G06T1/20 , G06T1/60 , G09G5/36 , G09G5/393 , G11C5/00 , G11C11/401 , G11C11/407
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G09G5/399
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

8. 发明授权

US08332683B2 Data processing system and image processing system 失效
标题翻译：数据处理系统和图像处理系统
公开(公告)号：US08332683B2
公开(公告)日：2012-12-11
申请号：US12731442
申请日：2010-03-25
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/04
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译：一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

9. 发明授权

US07711976B2 Data processing system and image processing system 失效
标题翻译：数据处理系统和图像处理系统
公开(公告)号：US07711976B2
公开(公告)日：2010-05-04
申请号：US11826136
申请日：2007-07-13
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/04
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译：一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

10. 发明授权

US06600492B1 Picture processing apparatus and picture processing method 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US06600492B1
公开(公告)日：2003-07-29
申请号：US09292375
申请日：1999-04-15
申请人： Tetsuya Shimomura , Shigeru Matsuo , Kazuyoshi Koga , Koyo Katsura , Yasuhiro Nakatsuka , Kazushige Yamagishi
发明人： Tetsuya Shimomura , Shigeru Matsuo , Kazuyoshi Koga , Koyo Katsura , Yasuhiro Nakatsuka , Kazushige Yamagishi
IPC分类号： G06T1500
CPC分类号： G06T1/60
摘要： In order to assure that a plurality of circuits such as a CPU I/F circuit, a rendering circuit, a video input circuit and a display circuit, which are each required to always complete a processing within a prescribed time, are each assured the ability to make as many accesses to a memory as required to complete the processing within the prescribed time, it is necessary to arbitrate a contention for an access to the memory through an internal bus among the circuits by employing a bus control circuit wherein priority levels assigned to the circuits to make an access to the internal bus are dynamically changed by comparing degrees of access urgency among the circuits. In this way, circuits that each have to always complete theirs processing within a prescribed time are assured the ability to make as many accesses to the memory as required to complete the processing within the prescribed time even if a plurality of such circuits do exist.
摘要翻译：为了确保在规定时间内需要总是完成处理的多个电路，例如CPU I / F电路，再现电路，视频输入电路和显示电路，都能确保能力为了在规定的时间内对存储器进行尽可能多的访问以完成处理，有必要通过使用总线控制电路来通过内部总线来仲裁访问存储器的争用，其中优先级分配给通过比较电路之间的访问紧急程度来动态地改变访问内部总线的电路。以这种方式，每个必须总是在规定时间内完成它们的处理的电路确保了即使存在多个这样的电路，也可以在规定的时间内完成处理所需的存储器的访问的能力。

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