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41. 发明授权

US07291556B2 Method for forming small features in microelectronic devices using sacrificial layers 失效
标题翻译：在使用牺牲层的微电子器件中形成小特征的方法
公开(公告)号：US07291556B2
公开(公告)日：2007-11-06
申请号：US10873388
申请日：2004-06-22
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
摘要翻译：在微电子基板的区域上形成介电层。在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。在牺牲层和开口中形成导电层。去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并且在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。还讨论了通过这种技术形成的相变存储器件。

42. 发明申请

US20050263823A1 Phase-change memory device having a barrier layer and manufacturing method 有权
标题翻译：具有阻挡层的相变存储器件和制造方法
公开(公告)号：US20050263823A1
公开(公告)日：2005-12-01
申请号：US11027255
申请日：2004-12-30
申请人： Young-Nam Hwang , Gwan-Hyeob Koh , Su-Jin Ahn , Sung-Lae Cho , Se-Ho Lee , Kyung-Chang Ryoo , Chang-Wook Jeong , Su-Youn Lee , Bong-Jin Kuh
发明人： Young-Nam Hwang , Gwan-Hyeob Koh , Su-Jin Ahn , Sung-Lae Cho , Se-Ho Lee , Kyung-Chang Ryoo , Chang-Wook Jeong , Su-Youn Lee , Bong-Jin Kuh
IPC分类号： H01L27/108 , H01L27/24 , H01L45/00
CPC分类号： H01L29/7843 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666
摘要： A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.
摘要翻译：相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。模制层具有从其顶表面垂直延伸的突出部分。该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

43. 发明申请

US20050215009A1 Methods of forming phase-change memory devices 审中-公开
标题翻译：形成相变存储器件的方法
公开(公告)号：US20050215009A1
公开(公告)日：2005-09-29
申请号：US11084274
申请日：2005-03-18
申请人： Sung-Lae Cho
发明人： Sung-Lae Cho
IPC分类号： H01L27/115 , G11B5/127 , G11B5/33 , H01L21/00 , H01L21/336 , H01L45/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/1683
摘要： A method of forming a phase-change non-volatile memory device can include etching-back a spacer insulating layer using a fluorine-based etch gas to form a spacer pattern in an opening in an interlayer dielectric layer and etching the spacer insulating layer in the opening using an inert gas.
摘要翻译：形成相变非易失性存储器件的方法可以包括使用氟基蚀刻气体来蚀刻间隔绝缘层，以在层间电介质层的开口中形成间隔物图案，并且蚀刻间隔绝缘层使用惰性气体打开。

44. 发明授权

US08625325B2 Memory cells including resistance variable material patterns of different compositions 有权
标题翻译：记忆单元包括不同组成的电阻变化材料图案
公开(公告)号：US08625325B2
公开(公告)日：2014-01-07
申请号：US12853329
申请日：2010-08-10
申请人： Hyeong-Geun An , Ik-Soo Kim , Hee-Ju Shin , Dong-Hyun Im , Sung-Lae Cho , Eun-Hee Cho
发明人： Hyeong-Geun An , Ik-Soo Kim , Hee-Ju Shin , Dong-Hyun Im , Sung-Lae Cho , Eun-Hee Cho
IPC分类号： G11C11/56
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0092 , G11C2213/56 , G11C2213/72 , H01L27/101
摘要： A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected in series between first and second electrodes. A material composition of the first resistance variable pattern is different than a material composition of the second resistance variable pattern. Multi-bit data states of each memory cell are defined by a contiguous increase in size of a programmable high-resistance volume within the first and second resistance variable patterns.
摘要翻译：非易失性存储器件包括多个字线，多个位线，以及每个电连接在相应字线和相应位线之间的可变电阻存储单元阵列。每个存储单元包括在第一和第二电极之间串联电连接的第一和第二电阻可变图案。第一电阻可变图案的材料组成不同于第二电阻变化图案的材料组成。每个存储器单元的多位数据状态由第一和第二电阻变化模式内的可编程高电阻体积的连续增加来定义。

45. 发明授权

US08580606B2 Method of forming resistance variable memory device 有权
标题翻译：形成电阻变量存储器件的方法
公开(公告)号：US08580606B2
公开(公告)日：2013-11-12
申请号：US13241315
申请日：2011-09-23
申请人： Jeong-Hee Park , Jung-Hwan Park , Hideki Horii , Sung-Lae Cho
发明人： Jeong-Hee Park , Jung-Hwan Park , Hideki Horii , Sung-Lae Cho
IPC分类号： H01L21/06
CPC分类号： H01L45/1625 , H01L27/2409 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A method of forming a resistance variable memory device, the method including forming a diode on a semiconductor substrate; forming a lower electrode on the diode; forming a first insulating film on the lower electrode, the first insulating film having an opening; forming a resistance variable film filling the opening such that the resistance variable film includes an amorphous region adjacent to a sidewall of the opening and a crystalline region adjacent to the lower electrode; and forming an upper electrode on the resistance variable film.
摘要翻译：一种形成电阻可变存储器件的方法，所述方法包括在半导体衬底上形成二极管; 在二极管上形成下电极; 在所述下电极上形成第一绝缘膜，所述第一绝缘膜具有开口; 形成填充所述开口的电阻变化膜，使得所述电阻变化膜包括与所述开口的侧壁相邻的非晶区域和与所述下部电极相邻的结晶区域; 并在电阻变化膜上形成上电极。

46. 发明授权

US08026543B2 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US08026543B2
公开(公告)日：2011-09-27
申请号：US12338814
申请日：2008-12-18
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L27/108 , H01L47/00
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.
摘要翻译：相变存储器件具有氧化阻挡层以防止存储器细胞污染或氧化。在一个实施例中，半导体存储器件包括设置在半导体衬底上的成型层，相变材料图案和电绝缘材料的氧化屏障。成型层在其上部具有突出部。可相变材料图案的一部分覆盖模制层的突起，并且相变材料图案的另一部分延伸穿过突出部。氧化屏障的电绝缘材料可以覆盖相变材料图案和/或延伸并且覆盖模制层的突起和设置在突起上的相变材料图案的部分邻接的整个区域。

47. 发明申请

US20110032753A1 MEMORY CELLS INCLUDING RESISTANCE VARIABLE MATERIAL PATTERNS OF DIFFERENT COMPOSITIONS 有权
标题翻译：包含不同成分的电阻变化材料的记忆细胞
公开(公告)号：US20110032753A1
公开(公告)日：2011-02-10
申请号：US12853329
申请日：2010-08-10
申请人： Hyeong-Geun An , Ik-Soo Kim , Hee-Ju Shin , Dong-Hyun Im , Sung-Lae Cho , Eun-Hee Cho
发明人： Hyeong-Geun An , Ik-Soo Kim , Hee-Ju Shin , Dong-Hyun Im , Sung-Lae Cho , Eun-Hee Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0092 , G11C2213/56 , G11C2213/72 , H01L27/101
摘要： A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected in series between first and second electrodes. A material composition of the first resistance variable pattern is different than a material composition of the second resistance variable pattern. Multi-bit data states of each memory cell are defined by a contiguous increase in size of a programmable high-resistance volume within the first and second resistance variable patterns.
摘要翻译：非易失性存储器件包括多个字线，多个位线，以及每个电连接在相应字线和相应位线之间的可变电阻存储单元阵列。每个存储单元包括在第一和第二电极之间串联电连接的第一和第二电阻可变图案。第一电阻可变图案的材料组成不同于第二电阻变化图案的材料组成。每个存储器单元的多位数据状态由第一和第二电阻变化模式内的可编程高电阻体积的连续增加来定义。

48. 发明授权

US07485559B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07485559B2
公开(公告)日：2009-02-03
申请号：US11149153
申请日：2005-06-10
申请人： Sung-Lae Cho , Horii Hideki
发明人： Sung-Lae Cho , Horii Hideki
IPC分类号： H01L21/44
CPC分类号： H01L21/76886 , H01L27/115 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A semiconductor device and methods thereof. The semiconductor device includes a first layer formed on a substrate, the first layer having a higher conductivity. The semiconductor device further includes a second layer formed on the first layer, the second layer including a hole exposing a portion of the first layer, the exposed portion of the first layer having a lower conductivity. The method includes forming a first layer on a substrate, the first layer having a higher conductivity, forming a second layer on the first layer, exposing a portion of the first layer by forming a hole in the second layer, performing a process on at least the exposed portion of the first layer, the process decreasing the conductivity of the exposed portion. The exposed portion including the lower conductivity or higher resistivity may block heat from conducting in the first layer.
摘要翻译：半导体器件及其方法。半导体器件包括形成在衬底上的第一层，第一层具有较高的导电性。半导体器件还包括形成在第一层上的第二层，第二层包括暴露第一层的一部分的孔，第一层的暴露部分具有较低的导电性。该方法包括在衬底上形成第一层，第一层具有较高的导电性，在第一层上形成第二层，通过在第二层中形成孔露出第一层的一部分，至少执行一个工艺第一层的暴露部分，该工艺降低了暴露部分的导电性。包括较低电导率或较高电阻率的暴露部分可阻止第一层中导热的热量。

49. 发明授权

US07473597B2 Method of forming via structures and method of fabricating phase change memory devices incorporating such via structures 有权
标题翻译：形成通孔结构的方法和制造包含这种通孔结构的相变存储器件的方法
公开(公告)号：US07473597B2
公开(公告)日：2009-01-06
申请号：US11201421
申请日：2005-08-11
申请人： Jang-Eun Lee , Sung-Lae Cho , Jeong-Hee Park
发明人： Jang-Eun Lee , Sung-Lae Cho , Jeong-Hee Park
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： Provided are methods for forming conductive plug structures, such as via plugs, from a plurality of conductive layer patterns and methods of fabricating semiconductor devices, including semiconductor memory devices such as phase change semiconductor memory devices. An example method forms a small via structure by forming a conductive layer on a semiconductor substrate. A molding insulating layer is formed on the conductive layer and a via hole is formed through the insulating layer to expose a region of the conductive layer. A first via filling layer is formed and then partially removed to form a partial via plug. The formation and removal of the phase change material layer are then repeated as necessary to form a multilayer plug structure that substantially fills the via hole with the multilayer structure typically exhibiting reduced defects and damage than plug structures prepared by conventional methods.
摘要翻译：提供了用于从多个导电层图案形成诸如通孔插头的导电插塞结构的方法以及制造半导体器件的方法，包括诸如相变半导体存储器件的半导体存储器件。示例性方法通过在半导体衬底上形成导电层来形成小通孔结构。在导电层上形成模制绝缘层，并且通过绝缘层形成通孔以暴露导电层的区域。形成第一通孔填充层，然后部分地移除以形成部分通孔塞。然后根据需要重复形成和除去相变材料层以形成多层插塞结构，该多层插塞结构基本上填充通孔，其中多层结构通常表现出比通过常规方法制备的插塞结构减少的缺陷和损伤。

50. 发明申请

US20080016675A1 Methods of Forming Magnetic Memory Devices Including Ferroelectric Spacers 有权
标题翻译：形成包含铁电隔离器的磁存储器件的方法
公开(公告)号：US20080016675A1
公开(公告)日：2008-01-24
申请号：US11776625
申请日：2007-07-12
申请人： Kyung-Rae Byun , Sung-Lae Cho
发明人： Kyung-Rae Byun , Sung-Lae Cho
IPC分类号： H01F7/06 , G11B5/127 , H05K3/10
CPC分类号： H01L43/12 , G11C11/16 , H01L27/228 , H01L43/08 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49048 , Y10T29/49052 , Y10T29/49155
摘要： A magnetic memory device may include a digit line on a substrate, a first insulating layer on the digit line, and a magnetic tunnel junction memory cell on the first insulating layer so that the first insulating layer is between the digit line and the magnetic tunnel junction memory cell. A second insulating layer may be provided on the magnetic tunnel junction memory cell, wherein the second insulating layer has a hole therein exposing portions of the magnetic tunnel junction memory cell. A bit line may be provided on the second insulating layer and on portions of the magnetic tunnel junction memory cell exposed by the hole in the second insulating layer, and ferromagnetic spacers may be provided on sidewalls of at least one of the digit line and/or the bit line. Related methods are also discussed.
摘要翻译：磁存储器件可以包括衬底上的数字线，数字线上的第一绝缘层和第一绝缘层上的磁性隧道结存储单元，使得第一绝缘层位于数字线和磁性隧道结之间记忆单元第二绝缘层可以设置在磁性隧道结存储单元上，其中第二绝缘层在其中具有一个孔，暴露出磁性隧道结存储单元的部分。位线可以设置在第二绝缘层上以及在由第二绝缘层中的孔暴露的磁性隧道结存储单元的部分上，并且铁磁间隔物可以设置在数字线和/或其中的至少一个的侧壁上位线。还讨论了相关方法。

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