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41. 发明授权

US08129815B2 High-voltage transistor device with integrated resistor 有权
公开(公告)号：US08129815B2
公开(公告)日：2012-03-06
申请号：US12583426
申请日：2009-08-20
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/80 , H01L27/105
CPC分类号： H01L29/808 , H01L27/0629 , H01L28/20 , H01L29/0634 , H01L29/1058 , H01L29/1066
摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

42. 发明授权

US07732860B2 Gate metal routing for transistor with checkerboarded layout 有权
标题翻译：晶体管的栅极金属布线，具有棋盘布局
公开(公告)号：US07732860B2
公开(公告)日：2010-06-08
申请号：US12291569
申请日：2008-11-12
申请人： Vijay Parthasarathy
发明人： Vijay Parthasarathy
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42372 , H01L29/4238
摘要： In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管被布置成细长晶体管段的部分。这些部分基本上跨越半导体管芯排列成行和列。一行或一列的相邻部分定向成使得相邻部分中的第一个部分中的晶体管段的长度在第一方向上延伸，并且相邻部分中的第二个中的晶体管段的长度在第二方向，第一方向基本上与第二方向正交。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

43. 发明申请

US20100065903A1 High-voltage vertical transistor with a varied width silicon pillar 有权
标题翻译：具有不同宽度硅柱的高压立式晶体管
公开(公告)号：US20100065903A1
公开(公告)日：2010-03-18
申请号：US12284086
申请日：2008-09-18
申请人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
发明人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
IPC分类号： H01L47/00
CPC分类号： H01L29/7802 , H01L29/0657 , H01L29/0696 , H01L29/407 , H01L29/4238 , H01L29/7397 , H01L29/7813 , H01L29/872
摘要： In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.
摘要翻译：在一个实施例中，垂直HVFET包括半导体材料的柱状半导体材料的柱，其布置成具有至少两个具有第一宽度的至少两个基本上平行且基本上线性的圆角部分的环形布局，以及至少两个圆形部分，具有比第一宽度窄的第二宽度，第一导电类型的源极区域设置在柱的顶表面处或附近，并且第二导电类型的主体区域设置在源极区域下方的柱中。第一和第二电介质区域分别设置在柱的相对侧上，第一介质区域被柱侧向包围，第二介质区域横向围绕柱。第一和第二场板分别设置在第一和第二电介质区域中。

44. 发明申请

US20090315105A1 High-voltage vertical transistor structure 有权
标题翻译：高压立式晶体管结构
公开(公告)号：US20090315105A1
公开(公告)日：2009-12-24
申请号：US12583745
申请日：2009-08-25
申请人： Vijay Parthasarathy , Martin H. Manley
发明人： Vijay Parthasarathy , Martin H. Manley
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7811 , H01L2924/13055 , H01L2924/19043
摘要： In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，晶体管包括以跑道形布置布置的半导体材料柱，其具有在第一横向方向上延伸的基本上线性的部分，并且在基本线性部分的每个端部处具有圆形部分。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。分别设置在第一和第二电介质区域中的第一和第二栅极部件通过在基本线性部分中具有第一厚度的栅极氧化物与柱分离。栅极氧化物在圆形部分处基本上更厚。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

45. 发明申请

US20090273023A1 Segmented pillar layout for a high-voltage vertical transistor 失效
标题翻译：用于高压垂直晶体管的分段柱布局
公开(公告)号：US20090273023A1
公开(公告)日：2009-11-05
申请号：US12455462
申请日：2009-06-02
申请人： Vijay Parthasarathy , Wayne Bryan Grabowski
发明人： Vijay Parthasarathy , Wayne Bryan Grabowski
IPC分类号： H01L29/78 , H01L29/06 , H01L27/088
CPC分类号： H01L27/088 , H01L21/77 , H01L23/562 , H01L29/0607 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。邻接第一和第二部分的晶体管段的外场板被分离或部分合并。

46. 发明申请

US20060202265A1 Process insensitive ESD protection device 有权
标题翻译：过程不敏感的ESD保护装置
公开(公告)号：US20060202265A1
公开(公告)日：2006-09-14
申请号：US11078026
申请日：2005-03-11
申请人： Hongzhong Xu , Richard Ida , Vijay Parthasarathy
发明人： Hongzhong Xu , Richard Ida , Vijay Parthasarathy
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.
摘要翻译：提供了LDMOS器件的ESD保护方法和设备。该装置包括两个LDMOS器件，源极，漏极和栅极触点并联耦合。一个是受保护的设备，另一个是保护设备。每个具有源极区，漏极区，栅极，包含源极的第一体阱区域，含有漏极的第二体阱区域和通过漂移区域与第一体阱区域分离的隔离区域，与第一和第二体阱区域分离的隔离区域以及与隔离区域接触的掩埋层。保护装置具有与漏极相同类型的另一区域，将漏极耦合到隔离区域。其漏极连接通过与其隔离区而不是漏极区的接触进行。保护装置的漂移区域希望更小，并且隔离体阱分离比对于受保护的装置大。

47. 发明申请

US20060120874A1 Stacked lamellate assembly 有权
标题翻译：堆叠层状组件
公开(公告)号：US20060120874A1
公开(公告)日：2006-06-08
申请号：US11031797
申请日：2005-01-07
申请人： Michael Burke , Jay Morrison , Steven Vance , Daniel Thompson , Vijay Parthasarathy , Gary Merrill , Douglas Keller
发明人： Michael Burke , Jay Morrison , Steven Vance , Daniel Thompson , Vijay Parthasarathy , Gary Merrill , Douglas Keller
IPC分类号： F04D29/38
CPC分类号： F01D5/147 , F01D5/284 , F04D29/388 , F05D2230/23 , F05D2300/601 , F05D2300/603 , F05D2300/614
摘要： A stacked ceramic matrix composite lamellate assembly (10) including shear force bearing structures (48) for resisting relative sliding movement between adjacent lamellae. The shear force bearing structures may take the form of a cross-lamellar stitch (50), a shear pin (62), a warp (90) in the lamellae, a tongue (104) and groove (98) structure, or an inter-lamellar sealing member (112), in various embodiments. Each shear force bearing structure secures a subset of the lamellae, with at least one lamella being common between adjacent subsets in order to secure the entire assembly.
摘要翻译：一种层叠的陶瓷基复合材料层状组件（10），其包括用于抵抗相邻薄片之间的相对滑动运动的剪切力轴承结构（48）。剪切力承载结构可以采取跨层状缝合（50），剪切销（62），薄片中的经线（90），舌状物（104）和凹槽（98）结构的形式， - 绝缘密封件（112）。每个剪切力轴承结构确保薄片的一个子集，其中至少一个薄片在相邻子集之间是共同的，以便固定整个组件。

48. 发明授权

US6110804A Method of fabricating a semiconductor device having a floating field conductor 失效
标题翻译：制造具有浮动场导体的半导体器件的方法
公开(公告)号：US6110804A
公开(公告)日：2000-08-29
申请号：US887718
申请日：1997-07-07
申请人： Vijay Parthasarathy , Michael J. Zunino , William R. Peterson , Shang-Hui Tu
发明人： Vijay Parthasarathy , Michael J. Zunino , William R. Peterson , Shang-Hui Tu
IPC分类号： H01L29/06 , H01L29/40 , H01L29/78 , H01L21/76
CPC分类号： H01L29/404 , H01L29/7835
摘要： A semiconductor device (10) uses a plurality of floating field conductors (26, 28) to provide a substantially uniform electric field along the surface of the drift region (17) of the device (10). This substantially uniform electric field increases the breakdown voltage per unit length of the drift region (17).
摘要翻译：半导体器件（10）使用多个浮动场导体（26,28）沿着器件（10）的漂移区域（17）的表面提供基本均匀的电场。该基本上均匀的电场增加漂移区（17）的每单位长度的击穿电压。

49. 发明授权

US09601613B2 Gate pullback at ends of high-voltage vertical transistor structure 有权
公开(公告)号：US09601613B2
公开(公告)日：2017-03-21
申请号：US13541965
申请日：2012-07-05
申请人： Vijay Parthasarathy , Martin H. Manley
发明人： Vijay Parthasarathy , Martin H. Manley
IPC分类号： H01L29/06 , H01L29/423 , H01L29/78 , H01L29/40 , H01L21/77 , H01L29/08 , H01L29/417
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7811 , H01L2924/13055 , H01L2924/19043
摘要： In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

50. 发明授权

US09259155B2 Method to estimate interfractional and intrafractional organ motion for adaptive external beam radiotherapy 有权
$Method to estimate interfractional and intrafractional organ motion for adaptive external beam radiotherapy$
标题翻译：估计自适应外束放射治疗的内分泌和内分泌器官运动的方法
公开(公告)号：US09259155B2
公开(公告)日：2016-02-16
申请号：US14237227
申请日：2012-07-24
申请人： Shyam Bharat , Vijay Parthasarathy
发明人： Shyam Bharat , Vijay Parthasarathy
IPC分类号： G01T1/08 , A61N5/10 , A61B5/00 , A61B5/11
CPC分类号： A61B5/0033 , A61B5/1126 , A61B5/721 , A61B2562/0233 , A61N5/103 , A61N5/1037 , A61N5/1038 , A61N5/1039 , A61N5/1049 , A61N5/1071 , A61N2005/1051 , A61N2005/1072 , G01T1/08 , G06T2207/30004
摘要： A therapy system (10) includes one or more processors (98, 100). The processors (98, 100) are programmed to receive one or more of: (1) dosimetric data from dosimeters (26, 28, 202, 204, 206, 208, 210, 212) implanted within a patient and/or positioned on a vest (200); and (2) motion data from surrogates (18, 20, 22, 24) implanted within the patient. Based on the motion data, a current location and/or shape of a surrogate (18, 20, 22, 24) is determined and deviations between the current location and/or shape and a reference location and/or shape are determined. Based on the dosimetric data, a delivered dose distribution is compared with a planned dose distribution and deviations therebetween are determined. The deviations determined from the motion data and/or the dosimetric data are employed for adaptive planning, alignment, post treatment analysis, and safety.
摘要翻译：治疗系统（10）包括一个或多个处理器（98,100）。处理器（98,100）被编程为接收以下中的一个或多个：（1）植入患者体内和/或定位在患者体内的剂量计（26,28,202,204,206,208,210,212）的剂量测量数据背心（200）; 和（2）植入患者体内的替代物（18,20,22,24）的运动数据。基于运动数据，确定代理（18,20,22,24）的当前位置和/或形状，并且确定当前位置和/或形状与参考位置和/或形状之间的偏差。基于剂量学数据，将递送的剂量分布与计划的剂量分布进行比较，并确定它们之间的偏差。采用运动数据和/或剂量测量数据确定的偏差用于自适应规划，对准，后处理分析和安全性。

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