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1. 发明申请

US20090273023A1 Segmented pillar layout for a high-voltage vertical transistor 失效
标题翻译：用于高压垂直晶体管的分段柱布局
公开(公告)号：US20090273023A1
公开(公告)日：2009-11-05
申请号：US12455462
申请日：2009-06-02
申请人： Vijay Parthasarathy , Wayne Bryan Grabowski
发明人： Vijay Parthasarathy , Wayne Bryan Grabowski
IPC分类号： H01L29/78 , H01L29/06 , H01L27/088
CPC分类号： H01L27/088 , H01L21/77 , H01L23/562 , H01L29/0607 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。邻接第一和第二部分的晶体管段的外场板被分离或部分合并。

2. 发明授权

US07816731B2 Segmented pillar layout for a high-voltage vertical transistor 有权
标题翻译：用于高压垂直晶体管的分段柱布局
公开(公告)号：US07816731B2
公开(公告)日：2010-10-19
申请号：US12321250
申请日：2009-01-20
申请人： Vijay Parthasarathy , Wayne Bryan Grabowski
发明人： Vijay Parthasarathy , Wayne Bryan Grabowski
IPC分类号： H01L29/78
CPC分类号： H01L27/088 , H01L21/77 , H01L23/562 , H01L29/0607 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。邻接第一和第二部分的晶体管段的外场板被分离或部分合并。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

3. 发明申请

US20080197417A1 Segmented pillar layout for a high-voltage vertical transistor 有权
标题翻译：用于高压垂直晶体管的分段柱布局
公开(公告)号：US20080197417A1
公开(公告)日：2008-08-21
申请号：US11707406
申请日：2007-02-16
申请人： Vijay Parthasarathy , Wayne Bryan Grabowski
发明人： Vijay Parthasarathy , Wayne Bryan Grabowski
IPC分类号： H01L29/78
CPC分类号： H01L27/088 , H01L21/77 , H01L23/562 , H01L29/0607 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。邻接第一和第二部分的晶体管段的外场板被分离或部分合并。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

4. 发明授权

US08552493B2 Segmented pillar layout for a high-voltage vertical transistor 失效
公开(公告)号：US08552493B2
公开(公告)日：2013-10-08
申请号：US12455462
申请日：2009-06-02
申请人： Vijay Parthasarathy , Wayne Bryan Grabowski
发明人： Vijay Parthasarathy , Wayne Bryan Grabowski
IPC分类号： H01L29/78
CPC分类号： H01L27/088 , H01L21/77 , H01L23/562 , H01L29/0607 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

5. 发明授权

US07557406B2 Segmented pillar layout for a high-voltage vertical transistor 有权
公开(公告)号：US07557406B2
公开(公告)日：2009-07-07
申请号：US11707406
申请日：2007-02-16
申请人： Vijay Parthasarathy , Wayne Bryan Grabowski
发明人： Vijay Parthasarathy , Wayne Bryan Grabowski
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/77 , H01L23/562 , H01L29/0607 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

6. 发明申请

US20090134457A1 Segmented pillar layout for a high-voltage vertical transistor 有权
标题翻译：用于高压垂直晶体管的分段柱布局
公开(公告)号：US20090134457A1
公开(公告)日：2009-05-28
申请号：US12321250
申请日：2009-01-20
申请人： Vijay Parthasarathy , Wayne Bryan Grabowski
发明人： Vijay Parthasarathy , Wayne Bryan Grabowski
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/77 , H01L23/562 , H01L29/0607 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。邻接第一和第二部分的晶体管段的外场板被分离或部分合并。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

7. 发明授权

US10376179B2 MPR slice selection for visualization of catheter in three-dimensional ultrasound 有权
公开(公告)号：US10376179B2
公开(公告)日：2019-08-13
申请号：US14113035
申请日：2012-04-19
申请人： Vijay Parthasarathy , Ameet Kumar Jain , Charles Ray Hatt, III , Amish N. Raval
发明人： Vijay Parthasarathy , Ameet Kumar Jain , Charles Ray Hatt, III , Amish N. Raval
IPC分类号： A61B5/05 , A61B5/06 , A61B8/08 , A61B6/12 , A61B6/00 , A61B8/00 , G06T15/08 , A61M25/01 , A61B34/20 , A61B17/00 , A61B90/00
摘要： A system employs an interventional tool (30), ultrasound imaging system and a multi-planar reformatting module (40). The interventional tool (30) has one or more image tracking points (31). The ultrasound imaging system includes an ultrasound probe (20) operable for generating an ultrasound volume image (22) of a portion or an entirety of the interventional tool (30) within an anatomical region. The multi-planar reformatting imaging module (40) generates two or more multi- planar reformatting images (41) of the interventional tool (30) within the anatomical region. A generation of the two multi-planar reformatting images (41) includes an identification of each image tracking point (31) within the ultrasound volume image (22), and a utilization of each identified image tracking point (31) as an origin of the multi-planar reformatting images (41).

8. 发明授权

US09993304B2 Visualization of catheter of three-dimensional ultrasound 有权
公开(公告)号：US09993304B2
公开(公告)日：2018-06-12
申请号：US13997800
申请日：2012-01-10
申请人： Pingkun Yan , Vijay Parthasarathy , Robert Manzke , Ameet Kumar Jain
发明人： Pingkun Yan , Vijay Parthasarathy , Robert Manzke , Ameet Kumar Jain
IPC分类号： A61B34/20 , A61B6/12 , A61B8/08 , A61B8/00
CPC分类号： A61B34/20 , A61B6/12 , A61B8/0883 , A61B8/466 , A61B8/483
摘要： An image-guided system includes an X-ray imaging device for generating one or more X-ray images illustrating a tool within an anatomical region, and an ultrasound imaging device for generating an ultrasound image illustrating the tool within the anatomical region. The image-guided system further includes a tool tracking device for visually tracking the tool within the anatomical region. In operation, the tool tracking device localizes a portion of the tool as located within the ultrasound image responsive to an identification of the portion of the tool as located within the X-ray image(s), and executes an image segmentation of an entirety of the tool as located within the ultrasound image relative to a localization of the portion of the tool as located within the ultrasound image.

9. 发明授权

US08653600B2 High-voltage monolithic schottky device structure 有权
标题翻译：高压单片肖特基器件结构
公开(公告)号：US08653600B2
公开(公告)日：2014-02-18
申请号：US13487025
申请日：2012-06-01
申请人： Vijay Parthasarathy
发明人： Vijay Parthasarathy
IPC分类号： H01L29/66
CPC分类号： H01L29/8725 , H01L29/0619 , H01L29/0692 , H01L29/36 , H01L29/407
摘要： A semiconductor device includes a pillar formed on a substrate of the same conductivity type. The pillar has a vertical thickness that extends from a top surface down to the substrate. The pillar extends in first and second lateral directions in a loop shape. First and second dielectric regions are disposed on opposite lateral sides of the pillar, respectively. First and second conductive field plates are respectively disposed in the first and second dielectric regions. A metal layer is disposed on the top surface of the pillar, the metal layer forming a Schottky diode with respect to the pillar. When the substrate is raised to a high-voltage potential with respect to both the metal layer and the first and second field plates, the first and second field plates functioning capacitively to deplete the pillar of charge, thereby supporting the high-voltage potential along the vertical thickness of the pillar.
摘要翻译：半导体器件包括形成在相同导电类型的衬底上的柱。该柱具有从顶部表面向下延伸到基底的垂直厚度。支柱以第一和第二横向方向呈环形延伸。第一和第二电介质区域分别设置在柱的相对侧面上。第一和第二导电场板分别设置在第一和第二电介质区域中。金属层设置在柱的顶表面上，金属层相对于柱形成肖特基二极管。当基板相对于金属层和第一和第二场板两者升高到高压电位时，第一和第二场板电容地起作用以耗尽柱的电荷，从而支持沿着柱的垂直厚度。

10. 发明申请

US20120273885A1 High-Voltage Transistor Structure with Reduced Gate Capacitance 有权
标题翻译：具有降低栅极电容的高压晶体管结构
公开(公告)号：US20120273885A1
公开(公告)日：2012-11-01
申请号：US13532583
申请日：2012-06-25
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/0882 , H01L29/42368
摘要： In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.
摘要翻译：在一个实施例中，高电压场效应晶体管（HVFET）包括覆盖第一阱区的场氧化物层，所述场氧化物层具有第一厚度并且在第二横向方向上从漏极区延伸到接近第二阱地区。栅极氧化物覆盖沟道区域并且具有在第一横向方向上的第二尺寸。栅极在第二横向方向上从源极区域延伸到场氧化物层的一部分，栅极通过栅极氧化物与沟道区域绝缘，栅极在第一横向尺寸上延伸超过HVFET的非有效区域超过栅极氧化物的第二维度，栅极通过场氧化物层与无源区域上的第一和第二阱区绝缘。

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