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41. 发明申请

US20100311252A1 OXYGEN PLASMA REDUCTION TO ELIMINATE PRECURSOR OVERFLOW IN BPTEOS FILM DEPOSITION 有权
标题翻译：消除BPTEOS膜沉积中前体溢出的氧气等离子体减少
公开(公告)号：US20100311252A1
公开(公告)日：2010-12-09
申请号：US12478493
申请日：2009-06-04
申请人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/283 , H01L21/285
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02271 , H01L21/0234 , H01L21/3105 , H01L21/76826
摘要： A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.
摘要翻译：一种包括在反应室中提供半导体衬底的方法; 将包括硅和氧的第一反应物，硼掺杂剂和磷掺杂剂流动到反应室中，使得在半导体衬底上沉积BPTEOS层; 阻止第一反应物，硼掺杂剂和磷掺杂剂流入反应室，使得磷掺杂剂和富含硼的掺杂剂的膜沉积在BPTEOS层上; 并且还原膜包括将膜暴露于O 2等离子体。

42. 发明申请

US20050253268A1 Method and structure for improving adhesion between intermetal dielectric layer and cap layer 审中-公开
标题翻译：提高金属间电介质层和覆盖层之间粘附性的方法和结构
公开(公告)号：US20050253268A1
公开(公告)日：2005-11-17
申请号：US10967009
申请日：2004-10-15
申请人： Shao-Ta Hsu , Kuo-Hsien Cheng , Shwang-Ming Jeng , Hung-Tsai Liu , Wei-Cheng Chu , Yu-Ku Lin , Ying-Lang Wang
发明人： Shao-Ta Hsu , Kuo-Hsien Cheng , Shwang-Ming Jeng , Hung-Tsai Liu , Wei-Cheng Chu , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/768 , H01L23/48 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor interconnect structure including a semiconductor substrate, a semiconductor active device formed in the substrate, a layer of low-k dielectric material, a first patterned conducting layer, a second patterned conducting layer, and a cap layer formed thereon. The low-k material layer is formed over the semiconductor device. The first conducting line is formed in the low-k material layer and connected to the semiconductor active device. The second conducting line is formed in the low-k material layer but not electrically connected to the semiconductor active device. The cap layer is formed over the low-k material layer, the first and second conducting lines. The cap layer includes silicon and carbon. Since the adhesion strength between the cap layer and the patterned conducting layer is greater than the adhesion strength between the cap layer and the low-k material layer, the addition of second patterned conducting layer would eliminate the overall possibility of delamination between the surface where cap layer is in contact with the low-k material and the first and the second patterned conducting layers.
摘要翻译：包括半导体衬底，形成在衬底中的半导体有源器件，低k电介质材料层，第一图案化导电层，第二图案化导电层和形成在其上的帽层的半导体互连结构。低k材料层形成在半导体器件上。第一导线形成在低k材料层中并连接到半导体有源器件。第二导线形成在低k材料层中，但不与半导体有源器件电连接。盖层形成在低k材料层，第一和第二导电线之上。盖层包括硅和碳。由于盖层和图案化导电层之间的粘合强度大于覆盖层和低k材料层之间的粘合强度，所以添加第二图案化导电层将消除在盖的表面之间的分层的总体可能性层与低k材料和第一和第二图案化导电层接触。

43. 发明授权

US06372645B1 Methods to reduce metal bridges and line shorts in integrated circuits 有权
标题翻译：降低集成电路中金属桥和线路短路的方法
公开(公告)号：US06372645B1
公开(公告)日：2002-04-16
申请号：US09439367
申请日：1999-11-15
申请人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu , Shih-Chi Lin , Ming-Jer Lee , Ying-Lang Wang , Yu-Ku Lin
发明人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu , Shih-Chi Lin , Ming-Jer Lee , Ying-Lang Wang , Yu-Ku Lin
IPC分类号： H01L2144
CPC分类号： H01L21/76838 , H01L21/32051
摘要： In the first option of the present invention, a semiconductor structure is provided and an overlying titanium nitride barrier layer is deposited thereon at about 100° C. At least Al and Cu is sputtered over the titanium nitride barrier layer from about 270 to 300° C. to form an Al—Cu alloy containing metal layer. The sputtered Al—Cu alloy containing metal layer is promptly cooled at a cooling rate greater than about 100° C./minute to a temperature below 200° C. to form a Al—Cu alloy containing metal layer having minimal CuAl2 grain growth. The semiconductor structure is removed from the cooling chamber and the semiconductor structure is processed further below 200° C. to form semiconductor device precursors. In the second option of the present invention, a semiconductor structure having an overlying barrier layer is provided. At least Al and Cu is sputtered over the barrier layer at a first temperature to form an Al—Cu alloy containing metal layer having CuAl2 grains of a first average size. The semiconductor structure is processed and then heated to a second temperature to dissolve the CuAl2 grains of a first average size then rapidly cooling to a third temperature whereby the CuAl2 grains formed have a second average size within the Al—Cu alloy containing metal layer. The second average size CuAl2 grains being less than the first average size CuAl2 grains.
摘要翻译：在本发明的第一种选择中，提供了一种半导体结构，并在其上沉积了大约100℃的上覆氮化钛阻挡层。至少Al和Cu溅射在氮化钛阻挡层上约270-300℃ 以形成含有金属层的Al-Cu合金。将溅射的含有Al-Cu合金的金属层以大于约100℃/分钟的冷却速度迅速冷却到低于200℃的温度，以形成含有最小CuAl 2晶粒生长的金属层的Al-Cu合金。将半导体结构从冷却室中移除，半导体结构进一步在200℃以下进行处理以形成半导体器件前体。在本发明的第二个选择中，提供了具有上覆阻挡层的半导体结构。在第一温度下至少将Al和Cu溅射在阻挡层上，以形成含有具有第一平均尺寸的CuAl 2晶粒的金属层的Al-Cu合金。将半导体结构加工，然后加热至第二温度以溶解第一平均尺寸的CuAl 2晶粒，然后快速冷却至第三温度，由此形成的CuAl 2晶粒在含有Al-Cu合金的金属层内具有第二平均尺寸。第二平均尺寸CuAl2晶粒小于第一平均尺寸CuAl2晶粒。

44. 发明授权

US09254548B2 Method of forming diamond conditioners for CMP process 有权
标题翻译：形成CMP工艺用金刚石调理剂的方法
公开(公告)号：US09254548B2
公开(公告)日：2016-02-09
申请号：US13455448
申请日：2012-04-25
申请人： Yen-Chang Chao , Kei-Wei Chen , Ying-Lang Wang
发明人： Yen-Chang Chao , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： B24B53/017 , B24D3/06 , B24D3/28 , B24D18/00
CPC分类号： B24B53/12 , B24B53/017 , B24D3/06 , B24D3/28 , B24D18/00
摘要： A method for making a conditioner disk used in a chemical mechanical polishing (CMP) process comprises applying a first layer of at least one binder over a substrate; disposing a plurality of diamond particles on the first layer of the at least one first binder at the plurality of locations; and fixing the plurality of diamond particles to the substrate by heating the substrate to a raised temperature and then cooling the substrate. The plurality of diamond particles disposed over the substrate are configured to provide a working diamond ratio higher than 50% when the conditioner disk is used in a CMP process.
摘要翻译：用于制造在化学机械抛光（CMP）工艺中使用的调节盘的方法包括在衬底上施加至少一种粘合剂的第一层; 在所述多个位置处在所述至少一个第一粘合剂的所述第一层上设置多个金刚石颗粒; 以及通过将衬底加热到升高的温度然后冷却衬底，将多个金刚石颗粒固定到衬底上。设置在基板上的多个金刚石颗粒被配置为当在CMP工艺中使用调节盘时，提供高于50％的工作金刚石比例。

45. 发明授权

US09120194B2 Apparatus for wafer grinding 有权
标题翻译：晶圆研磨设备
公开(公告)号：US09120194B2
公开(公告)日：2015-09-01
申请号：US13188028
申请日：2011-07-21
申请人： Kuo-Hsiu Wei , Kei-Wei Chen , Ying-Lang Wang , Chun-Ting Kuo
发明人： Kuo-Hsiu Wei , Kei-Wei Chen , Ying-Lang Wang , Chun-Ting Kuo
IPC分类号： B24B7/22 , B24D7/14
CPC分类号： B24B7/228 , B24D7/14
摘要： A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.
摘要翻译：砂轮包括具有第一附接谷物垫的外基部; 以及具有第二附着谷物垫的内框架; 以及由所述外基座和所述内框架共享的主轴，其中所述外基座和所述内框架中的至少一个可以沿着所述共享主轴轴线独立地移动; 并且其中所述外基座，所述内框架和所述共享主轴轴线都具有相同的中心。研磨系统包括上述砂轮和附接到共享主轴轴线的能够垂直移动的砂轮头，除了驱动砂轮旋转的马达之外，以及用于将晶片固定在卡盘台顶部的卡盘台; 其中所述砂轮与所述卡盘台的一部分重叠，所述卡盘台的每一个能够沿相反方向旋转。

46. 发明授权

US09064770B2 Methods for minimizing edge peeling in the manufacturing of BSI chips 有权
标题翻译： BSI芯片制造中边缘剥离最小化的方法
公开(公告)号：US09064770B2
公开(公告)日：2015-06-23
申请号：US13551457
申请日：2012-07-17
申请人： Chun-Ting Kuo , Kei-Wei Chen , Ying-Lang Wang , Kuo-Hsiu Wei
发明人： Chun-Ting Kuo , Kei-Wei Chen , Ying-Lang Wang , Kuo-Hsiu Wei
IPC分类号： H01L21/02 , H01L27/146
CPC分类号： H01L27/1464 , H01L21/02087 , H01L21/0209 , H01L27/14687
摘要： A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.
摘要翻译：一种方法包括在半导体衬底上形成顶部金属线，其中半导体衬底是具有斜面的晶片的一部分。当顶部金属线暴露时，在斜面上提供蚀刻剂，其中用蚀刻剂喷射的晶片的区域具有形成具有第一直径的第一环的内部限定线。进行修整步骤以修剪晶片的边缘部分，其中晶片的剩余部分的边缘具有基本上等于或小于第一直径的第二直径。

47. 发明授权

US08552529B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08552529B2
公开(公告)日：2013-10-08
申请号：US13488958
申请日：2012-06-05
申请人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
发明人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L21/02
CPC分类号： H01L27/0805 , H01L28/60 , H01L28/75
摘要： A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.
摘要翻译：公开了一种半导体器件。该装置包括基板; 覆盖衬底的第一金属层; 覆盖在第一金属层上的电介质层; 以及覆盖所述电介质层的第二金属层，其中所述第一金属层包括：第一体心立方晶格金属层; 第一底层，位于第一体心立方晶格金属层下面，其中第一底层是体心立方晶格的金属，包括钛（Ti），钨（W），钼（Mo）或铌（Nb）; 以及在第一体心立方晶格金属层和第一底层之间的体心立方晶格的第一界面。

48. 发明授权

US08551193B2 Nickel alloy target including a secondary metal 有权
标题翻译：镍合金靶包括二次金属
公开(公告)号：US08551193B2
公开(公告)日：2013-10-08
申请号：US13188182
申请日：2011-07-21
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen
IPC分类号： C22C19/03 , H01L21/283
CPC分类号： H01L29/45 , C23C14/14 , C23C14/3414 , H01L21/28052 , H01L21/28518 , H01L21/2855 , H01L21/823418 , H01L29/456 , H01L29/665 , Y10T29/41
摘要： A target includes nickel and a secondary metal. The secondary metal has a volume percentage between about 1 percent and about 10 percent. The secondary metal has a density between about 5,000 kg/m3 and about 15,000 kg/m3.
摘要翻译：目标包括镍和二次金属。次级金属的体积百分比在约1％至约10％之间。二次金属具有约5,000kg / m 3至约15,000kg / m 3的密度。

49. 发明申请

US20080211106A1 VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF 有权
标题翻译：威盛/联系人和丹麦结构及其制造方法
公开(公告)号：US20080211106A1
公开(公告)日：2008-09-04
申请号：US11680981
申请日：2007-03-01
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.
摘要翻译：形成半导体结构的方法包括在衬底上形成电介质层。在电介质层上形成第一非导电阻挡层。通过第一非导电阻挡层和介电层内形成至少一个开口。在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上的开幕。然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。

50. 发明授权

US08772899B2 Method and apparatus for backside illumination sensor 有权
标题翻译：背面照明传感器的方法和装置
公开(公告)号：US08772899B2
公开(公告)日：2014-07-08
申请号：US13409924
申请日：2012-03-01
申请人： Shiu-Ko JangJian , Min Hao Hong , Kei-Wei Chen , Ying-Lang Wang
发明人： Shiu-Ko JangJian , Min Hao Hong , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L31/00 , H01L31/02
CPC分类号： H01L27/1464 , H01L27/14687
摘要： Methods and apparatus for a backside illuminated (BSI) image sensor device are disclosed. A BSI sensor device is formed on a substrate comprising a photosensitive diode. The substrate may be thinned at the backside, then a B doped Epi-Si(Ge) layer may be formed on the backside surface of the substrate. Additional layers may be formed on the B doped Epi-Si(Ge) layer, such as a metal shield layer, a dielectric layer, a micro-lens, and a color filter.
摘要翻译：公开了用于背面照明（BSI）图像传感器装置的方法和装置。在包括感光二极管的基板上形成BSI传感器装置。衬底可以在背面变薄，则可以在衬底的背面上形成B掺杂的Epi-Si（Ge）层。另外的层可以形成在B掺杂的Epi-Si（Ge）层上，例如金属屏蔽层，电介质层，微透镜和滤色器。

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