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41. 发明申请

US20090029531A1 HYBRID ORIENTATION SUBSTRATE AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：混合方向衬底及其制造方法
公开(公告)号：US20090029531A1
公开(公告)日：2009-01-29
申请号：US12244944
申请日：2008-10-03
申请人： Haining S. Yang , Henry K. Utomo , Judson R. Holt
发明人： Haining S. Yang , Henry K. Utomo , Judson R. Holt
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L21/26533 , H01L21/823807 , H01L27/1203 , H01L29/045
摘要： A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.
摘要翻译：一种混合取向基片的制造方法，其特征在于：（1）使基底半导体衬底的一部分露出的被掩膜的表面半导体层的水平外延增强; 和（2）基底半导体衬底的暴露部分的垂直外延增加。所得到的表面半导体层和外延表面半导体层与不与基底半导体衬底垂直的界面邻接。该方法还包括通过表面半导体层和外延表面半导体层注入电介质形成离子，以提供将表面半导体层和外延表面半导体层与基底半导体衬底分离的掩埋电介质层。

42. 发明授权

US07482209B2 Hybrid orientation substrate and method for fabrication of thereof 失效
标题翻译：混合取向基板及其制造方法
公开(公告)号：US07482209B2
公开(公告)日：2009-01-27
申请号：US11559151
申请日：2006-11-13
申请人： Haining S. Yang , Henry K. Utomo , Judson R. Holt
发明人： Haining S. Yang , Henry K. Utomo , Judson R. Holt
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/26533 , H01L21/823807 , H01L27/1203 , H01L29/045
摘要： A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.
摘要翻译：一种混合取向基片的制造方法，其特征在于：（1）使基底半导体衬底的一部分露出的被掩膜的表面半导体层的水平外延增强; 和（2）基底半导体衬底的暴露部分的垂直外延增加。所得到的表面半导体层和外延表面半导体层与不与基底半导体衬底垂直的界面邻接。该方法还包括通过表面半导体层和外延表面半导体层注入电介质形成离子，以提供将表面半导体层和外延表面半导体层与基底半导体衬底分离的掩埋电介质层。

43. 发明申请

US20080251817A1 STRESSED FIELD EFFECT TRANSISTORS ON HYBRID ORIENTATION SUBSTRATE 失效
标题翻译：混合定向衬底上的应力场效应晶体管
公开(公告)号：US20080251817A1
公开(公告)日：2008-10-16
申请号：US12144250
申请日：2008-06-23
申请人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造它们的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

44. 发明申请

US20080164491A1 STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE 有权
标题翻译：具有硅酸盐的移动增强MOSFET的结构和方法
公开(公告)号：US20080164491A1
公开(公告)日：2008-07-10
申请号：US11619809
申请日：2007-01-04
申请人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
发明人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
摘要翻译：虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

45. 发明授权

US07388278B2 High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods 有权
标题翻译：具有应力诱导材料的SOI衬底上的高性能场效应晶体管作为掩埋绝缘体和方法
公开(公告)号：US07388278B2
公开(公告)日：2008-06-17
申请号：US11088595
申请日：2005-03-24
申请人： Judson R. Holt , Oiging C. Ouyang
发明人： Judson R. Holt , Oiging C. Ouyang
IPC分类号： H01L29/06
CPC分类号： H01L29/78 , H01L21/76254 , H01L27/1203 , H01L27/1207 , H01L29/7846
摘要： The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.
摘要翻译：本发明提供了一种半导体结构，其包括绝缘体（SOI）上的高性能场效应晶体管（FET），其绝缘体是预选几何形状的应力诱导材料。这种结构可以实现单轴应力的性能提高，并且通道中的应力不依赖于局部触点的布局设计。广义而言，本发明涉及一种包括上半导体层和底半导体层的半导体结构，其中所述上半导体层通过具有预选的应力诱导绝缘体在至少一个区域中与所述底部半导体层分离几何形状，所述应力诱导绝缘子在上半导体层上施加应变。

46. 发明申请

US20080087961A1 METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING 有权
标题翻译：通过退火减少堆叠不良的方法
公开(公告)号：US20080087961A1
公开(公告)日：2008-04-17
申请号：US11548428
申请日：2006-10-11
申请人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
发明人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
IPC分类号： H01L27/092 , H01L21/8232
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
摘要翻译：因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

47. 发明申请

US20070278585A1 CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS, AND METHODS FOR FABRICATING THE SAME USING FACETED EPITAXY 失效
标题翻译：具有混合信道方向的CMOS器件，以及使用面向外延制造其的方法
公开(公告)号：US20070278585A1
公开(公告)日：2007-12-06
申请号：US11422443
申请日：2006-06-06
申请人： Thomas W. Dyer , Sunfei Fang , Judson R. Holt
发明人： Thomas W. Dyer , Sunfei Fang , Judson R. Holt
IPC分类号： H01L29/94
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823821 , H01L21/823857 , H01L29/1037 , H01L29/78 , H01L29/7853
摘要： The present invention relates to a semiconductor substrate comprising at least first and second device regions. The first device region has a substantially planar surface oriented along one of a first set of equivalent crystal planes, and the second device region contains a protruding semiconductor structure having multiple intercepting surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, a first field effect transistor (FET) can be formed at the first device region, which comprises a channel that extends along the substantially planar surface of the first device region. A second, complementary FET can be formed at the second device region, while the second, complementary FET comprises a channel that extends along the multiple intercepting surfaces of the protruding semiconductor structure at the second device region.
摘要翻译：本发明涉及包括至少第一和第二器件区域的半导体衬底。第一器件区域具有沿着第一组等效晶面中的一个取向的基本平坦的表面，并且第二器件区域包含具有沿第二不同组的等效晶面取向的多个截止面的突出半导体结构。可以使用这种半导体衬底形成半导体器件结构。具体地，可以在第一器件区域处形成第一场效应晶体管（FET），该第一器件区域包括沿着第一器件区域的基本平坦的表面延伸的沟道。第二互补FET可以形成在第二器件区域，而第二互补FET包括在第二器件区域沿着突出半导体结构的多个截止表面延伸的沟道。

48. 发明授权

US08232186B2 Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure 失效
标题翻译：在PFET上对NFET和SiGe沟道反向eSiGe进行积分的方法及相关结构
公开(公告)号：US08232186B2
公开(公告)日：2012-07-31
申请号：US12128955
申请日：2008-05-29
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L21/20
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
摘要翻译：公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。作为选择，PFET区域上的SiGe层可能变薄。

49. 发明申请

US20120181631A1 METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING 有权
标题翻译：具有高K金属栅组合和SiGe通道工程的PMOS器件的方法和结构
公开(公告)号：US20120181631A1
公开(公告)日：2012-07-19
申请号：US13431328
申请日：2012-03-27
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
摘要翻译：公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄被提供。

50. 发明申请

US20120168775A1 STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING 失效
标题翻译：应力增强晶体管器件及其制造方法
公开(公告)号：US20120168775A1
公开(公告)日：2012-07-05
申请号：US13419164
申请日：2012-03-13
申请人： Johnathan E. Faltermeier , Judson R. Holt , Xuefeng Hua
发明人： Johnathan E. Faltermeier , Judson R. Holt , Xuefeng Hua
IPC分类号： H01L29/16 , H01L29/78
CPC分类号： H01L29/7849 , H01L29/66636 , H01L29/78
摘要： A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.
摘要翻译：晶体管器件包括通过栅极电介质在半导体衬底上间隔开的栅极导体，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，其中该沟道区域包括栅极下方的底切区域导体; 嵌入在栅极导体下方的沟道区域的底切区域中的应力材料; 并且外延生长的源极和漏极区域设置在半导体衬底的与应力材料横向相邻的凹陷区域中。

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