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41. 发明授权

US06249524B1 Cell buffer memory for a large capacity and high throughput ATM switch 失效
标题翻译：用于大容量和高吞吐量ATM交换机的单元缓冲存储器
公开(公告)号：US06249524B1
公开(公告)日：2001-06-19
申请号：US09044171
申请日：1998-03-19
申请人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
发明人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
IPC分类号： H04J324
CPC分类号： H04L49/108 , H04Q11/0478
摘要： Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.
摘要翻译：提供了一种高吞吐量大容量ATM交换机，其中在将DRAM用作ATM交换机的小区缓冲器的情况下产生的存储器访问时间和数据输出延迟时间的变化被吸收。为了实现这一点，ATM交换机包括使用用于存储单元的DRAM的第一存储器，使用SRAM的第二存储器，用于在将单元传送到第一存储器之前切换和临时存储单元;以及控制器，用于产生写/ 用于第一和第二存储器的定时信号。控制器产生用于第二存储器的读取地址和定时信号，并且基于第一存储器的存取地址来考虑第一存储器的存取时间或延迟时间的变化的写入地址和定时信号，从而在目的地输出将单元切换并存储在第二存储器中，然后存储在第一存储器中。

42. 发明授权

US5394397A Shared buffer memory type ATM communication system and method with a broadcast facility 失效
标题翻译：共享缓冲存储器类型ATM通信系统和方法与广播设施
公开(公告)号：US5394397A
公开(公告)日：1995-02-28
申请号：US38615
申请日：1993-03-29
申请人： Junichirou Yanagi , Yoshihiro Ashi , Takahiko Kozaki , Akihiko Takase , Takashi Nakashima
发明人： Junichirou Yanagi , Yoshihiro Ashi , Takahiko Kozaki , Akihiko Takase , Takashi Nakashima
IPC分类号： H04M3/42 , H04L12/18 , H04L12/761 , H04L12/931 , H04L12/951 , H04Q3/52 , H04Q11/04 , H04L12/56 , H04J3/26 , H04L12/48
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/203 , H04L49/309
摘要： An ATM switching system which includes an input interface which is provided every incoming line and serves to convert header information of each input cell into internal routing information, a shared buffer memory and a cell writing control unit which forms normal cell list structures, which are prepared in correspondence to outgoing lines and in which a plurality of normal cells are chained together with their next addresses, and a broadcast cell list structure, in which a plurality of broadcast cells are chained together with their next addresses, in the shared buffer memory, and serves to add successively the input cells to ones of the list structures, which are selected in correspondence to respective internal routing information. The invention also includes a cell reading control unit which serves to fetch selectively the cell from the list structures formed in the shared buffer memory to distribute the cell thus fetched to the associated outgoing lines. The cell reading control unit includes a broadcast destination table for "storing broadcast destination specifying information for specifying the outgoing lines, through which the broadcast cell is to be output, using a bit pattern, in correspondence to the internal routing information of the broadcast cell".
摘要翻译：一种ATM交换系统，其包括为每条输入线路提供的输入接口，用于将每个输入单元的头信息转换为内部路由信息，共享缓冲存储器和形成正常小区列表结构的小区写入控制单元，其被准备对应于输出线，并且其中多个正常小区与其下一个地址一起链接在一起，以及广播小区列表结构，其中多个广播小区与其下一个地址一起连接在共享缓冲存储器中，以及用于将输入单元连续地添加到与各个内部路由信息相对应地选择的列表结构中的一个。本发明还包括一个单元读取控制单元，用于从形成在共享缓冲存储器中的列表结构中选择性地提取单元，以将由此提取的单元分配到相关联的输出行。小区读取控制单元包括：广播目的地表，用于根据广播小区的内部路由信息，使用位模式存储用于指定要输出广播小区的出行的广播目的地指定信息; 。

43. 发明授权

US5315581A Hit-less protection switching method and apparatus for ATM transmission lines 失效
标题翻译：无线保护切换方法和ATM传输线路设备
公开(公告)号：US5315581A
公开(公告)日：1994-05-24
申请号：US744717
申请日：1991-08-14
申请人： Yukio Nakano , Akihiko Takase , Masahiro Takatori , Junichirou Yanagi
发明人： Yukio Nakano , Akihiko Takase , Masahiro Takatori , Junichirou Yanagi
IPC分类号： H04L1/22 , H04B1/74 , H04L12/70 , H04L12/801 , H04L12/911 , H04L29/14 , H04Q11/04 , H04L1/02
CPC分类号： H04L49/3081 , H04B1/74 , H04L69/40 , H04Q11/0478 , H04L2012/5627
摘要： A hit-less protection switching method and apparatus therefor for ATM transmission lines for selecting first cells from normal received signals and writing the same into a normal cell buffer, selecting second cells from emergency received signals and writing the same into an emergency cell buffer, reading the first cells from the normal cell buffer after a first delay time, reading the second cells from the emergency cell buffer after a second delay time, comparing the contents of the first cell with the contents of the second cell and changing the difference between the first delay time and the second delay time, when a state of discrepancy between the contents of the first cell and the contents of the second cell is continuously detected for a predetermined time, to dissolve the state of discrepancy, and selecting one of the cells read from the normal cell buffer and the emergency cell buffer with a delay as communications information.
摘要翻译：一种无线保护切换方法及其装置，用于ATM传输线路，用于从正常接收信号中选择第一小区并将其写入正常小区缓冲器，从紧急接收信号中选择第二小区并将其写入紧急小区缓冲器，读取在第一延迟时间之后，来自正常单元缓冲器的第一个单元，在第二延迟时间之后从紧急单元缓冲器读取第二单元，将第一单元的内容与第二单元的内容进行比较，并且改变第一单元延迟时间和第二延迟时间，当在预定时间内连续检测到第一单元的内容与第二单元的内容之间的差异的状态以解决差异的状态时，并且从正常小区缓冲区和具有延迟的紧急小区缓冲区作为通信信息。

44. 发明授权

US5283782A System switching method and apparatus without loss of signal in cell switching system of asynchronous transfer mode 失效
标题翻译：异步传输模式小区交换系统中系统切换方式和设备信号丢失
公开(公告)号：US5283782A
公开(公告)日：1994-02-01
申请号：US745332
申请日：1991-08-15
申请人： Akihiko Takase , Yoshihiro Ashi , Takashi Mori , Junichirou Yanagi
发明人： Akihiko Takase , Yoshihiro Ashi , Takashi Mori , Junichirou Yanagi
IPC分类号： H04L1/22 , H04L12/70 , H04L12/931 , H04L25/30 , H04Q11/04 , H04J1/16
CPC分类号： H04L49/105 , H04L49/153 , H04L49/552 , H04Q11/0478 , H04L2012/5627 , H04L49/1515
摘要： In a communication apparatus using an asynchronous transfer mode, there is provided a system switching method, and apparatus, without loss of signal for performing cell multiplexing or cell switching in a duplex system including a primary system and a standby system. In system switching, control information for switching between the primary system and the standby system is prepared. When a cell is inputted to the communication apparatus, the prepared control information is appended in a header portion of the cell. The cell with control information appended thereto is transmitted to the duplex system including the primary system and the standby system. On the basis of the control information, cell transfer of each system is controlled.
摘要翻译：在使用异步传送模式的通信装置中，提供了一种系统切换方法和装置，在包括主系统和备用系统的双工系统中，不丢失用于进行小区复用或小区切换的信号。在系统切换中，准备用于在主系统和备用系统之间切换的控制信息。当单元被输入到通信设备时，所准备的控制信息被附加在单元的报头部分中。具有附加控制信息的信元被发送到包括主系统和备用系统的双工系统。在控制信息的基础上，控制每个系统的单元传送。

45. 发明授权

US4967410A Method of multiplexing digital signals and apparatus therefor 失效
标题翻译：数字信号复用方法及其设备
公开(公告)号：US4967410A
公开(公告)日：1990-10-30
申请号：US324656
申请日：1989-03-17
申请人： Akihiko Takase , Yoshitaka Takasaki
发明人： Akihiko Takase , Yoshitaka Takasaki
IPC分类号： H04J3/00 , H04J3/06
CPC分类号： H04J3/0623
摘要： A high speed digital signal multiplexing method and apparatus are provided wherein a plurality of first higher bit rate transmission frames are provided, each first higher bit rate transmission frame being multiplexed therein with lower bit rate signals in an n-byte (n is an integer) interleave manner, and the lower bit rate signals are selectively derived from the plurality of first higher bit rate transmission frames and multiplexed into a second higher bit rate transmission frame. When a phase conflict is detected among the derived lower bit rate signals, all the data columns of at least one of the derived lower bit rate signals are given a predetermined delay by means of a shift register, and the derived signals are multiplexed into the second higher bit rate transmission frame. When a first higher bit rate transmission frame asynchronous with the system frame is detected, a pointer is derived which pointer represents a predetermined information unit within the derived lower bit rate signal. The derived pointer is inserted into a time slot corresponding to the frame pattern position of the second higher bit rate transmission frame for the lower bit rate signal. Thereafter, the derived signals are multiplexed.
摘要翻译：提供了一种高速数字信号复用方法和装置，其中提供多个第一较高比特率传输帧，每个第一高比特率传输帧在其中复用，其中n字节（n为整数）的较低比特率信号，并且从多个第一较高比特率传输帧中选择性地导出较低比特率信号，并被多路复用为第二较高比特率传输帧。当在导出的较低比特率信号中检测到相位冲突时，通过移位寄存器给出所导出的较低比特率信号中的至少一个的所有数据列，并将导出的信号复用到第二较高的比特率传输帧。当检测到与系统帧异步的第一较高比特率传输帧时，导出指针，该指针表示所导出的较低比特率信号内的预定信息单元。导出的指针被插入到与较低比特率信号的第二较高比特率传输帧的帧模式位置相对应的时隙中。此后，导出的信号被多路复用。

46. 发明申请

US20120089707A1 Virtual Network and Management Method of Virtual Network 审中-公开
标题翻译：虚拟网络的虚拟网络和管理方法
公开(公告)号：US20120089707A1
公开(公告)日：2012-04-12
申请号：US13208526
申请日：2011-08-12
申请人： Takashige Baba , Akihiko Takase
发明人： Takashige Baba , Akihiko Takase
IPC分类号： G06F15/177
CPC分类号： H04L41/046 , H04L41/022 , H04L41/0806 , H04L41/0853 , H04L45/04 , H04L45/60
摘要： There is a need to generate a virtual network across multiple physical networks without the need for users to understand information about the respective physical networks.A network system includes: multiple communication systems for communication with a user; multiple physical network management servers that manage multiple physical networks including multiple routers; and a virtual network management server that manages a virtual network connecting the communication systems with each other through the physical networks. The virtual network management server acquires physical network configuration information. The virtual network management server generates management information in order to manage the physical networks as one abstraction network. The virtual network management server configures the abstraction network by transmitting the generated management information to each of the physical network management servers and the routers.
摘要翻译：需要在多个物理网络之间生成虚拟网络，而不需要用户了解有关相应物理网络的信息。网络系统包括：用于与用户通信的多个通信系统; 多个物理网络管理服务器，管理多个物理网络，包括多个路由器; 以及虚拟网络管理服务器，其管理通过物理网络彼此连接通信系统的虚拟网络。虚拟网络管理服务器获取物理网络配置信息。虚拟网络管理服务器生成管理信息，以便将物理网络作为一个抽象网络进行管理。虚拟网络管理服务器通过将生成的管理信息发送到物理网络管理服务器和路由器中的每一个来配置抽象网络。

47. 发明申请

US20110029654A1 Service Control Device, Service Control System, and Method 有权
标题翻译：服务控制装置，服务控制系统和方法
公开(公告)号：US20110029654A1
公开(公告)日：2011-02-03
申请号：US12866396
申请日：2008-12-19
申请人： Yukiko Takeda , Akihiko Takase , Daisuke Matsubara
发明人： Yukiko Takeda , Akihiko Takase , Daisuke Matsubara
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L51/066 , H04L65/1006 , H04L65/105 , H04L65/1083 , H04L65/40 , H04L67/02 , H04M3/50 , H04M7/003 , H04M2203/2016
摘要： A communication entrepreneur has an application server 2 having message conversion function. The application server 2 performs service function distribution processing with reference to trigger rule 220 and message rule 230. The communication entrepreneur can provide various service functions without notifying individual server addresses to a service entrepreneur.
摘要翻译：通信企业家具有具有消息转换功能的应用服务器2。应用服务器2参照触发规则220和消息规则230执行服务功能分配处理。通信企业家可以提供各种服务功能，而不向服务企业家通知各个服务器地址。

48. 发明申请

US20080008091A1 Qos CONTROL SYSTEM 审中-公开
标题翻译： QOS控制系统
公开(公告)号：US20080008091A1
公开(公告)日：2008-01-10
申请号：US11764400
申请日：2007-06-18
申请人： Kazuma Yumoto , Akihiko Takase
发明人： Kazuma Yumoto , Akihiko Takase
IPC分类号： H04L12/56
CPC分类号： H04L47/24 , H04L47/15 , H04L47/70 , H04L47/745 , H04L47/748 , H04L47/781 , H04L47/822 , H04L47/824
摘要： A QoS control system for controlling allocation of a resource in a network, comprising: a terminal unit; a node unit for transferring a packet which is sent and to be received by the terminal unit; a resource requesting unit for requesting to allocate of a resource of the node unit; and a QoS control unit for controlling allocation of a resource of the node unit; in which the QoS control unit manages communication path information for transferring the packet received by the node unit, and resource information of the node unit, determines whether or not a node unit included in the communication path through which the terminal unit makes a communication can provide with a requested resource, and determines an alternative proposal of the requested resource when the node unit cannot provide with the requested resource, and notifies the resource requesting unit of the alternative proposal.
摘要翻译：一种用于控制网络中的资源分配的QoS控制系统，包括：终端单元; 节点单元，用于传送由终端单元发送和要接收的分组; 资源请求单元，用于请求分配节点单元的资源; 以及QoS控制单元，用于控制所述节点单元的资源的分配; 其中QoS控制单元管理用于传送由节点单元接收的分组的通信路径信息和节点单元的资源信息，确定包括在终端单元进行通信的通信路径中的节点单元是否可以提供并且当节点单元不能提供所请求的资源时，确定所请求的资源的替代方案，并且向资源请求单元通知替代提议。

49. 发明授权

US06463066B2 ATM switch 失效
标题翻译： ATM交换机
公开(公告)号：US06463066B2
公开(公告)日：2002-10-08
申请号：US09797696
申请日：2001-03-05
申请人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
发明人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
IPC分类号： H04J324
CPC分类号： H04L49/108 , H04Q11/0478
摘要： Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.
摘要翻译：提供了一种高吞吐量大容量ATM交换机，其中在将DRAM用作ATM交换机的小区缓冲器的情况下产生的存储器访问时间和数据输出延迟时间的变化被吸收。为了实现这一点，ATM交换机包括使用用于存储单元的DRAM的第一存储器，使用SRAM的第二存储器，用于在将单元传送到第一存储器之前切换和临时存储单元;以及控制器，用于产生写/ 用于第一和第二存储器的定时信号。控制器产生用于第二存储器的读取地址和定时信号，并且基于第一存储器的存取地址来考虑第一存储器的存取时间或延迟时间的变化的写入地址和定时信号，从而在目的地输出将单元切换并存储在第二存储器中，然后存储在第一存储器中。

50. 发明授权

US6034954A Multiplexing apparatus for transit of signals between service provided by low-speed transmission path and ATM service provided by high-speed transmission path 失效
标题翻译：由低速传输路径提供的服务之间的信号传输和由高速传输路径提供的ATM服务的多路复用装置
公开(公告)号：US6034954A
公开(公告)日：2000-03-07
申请号：US912057
申请日：1997-08-15
申请人： Akihiko Takase , Masahiro Takatori , Masaru Murakami , Kaori Nakayama , Hitoshi Yajima , Takaaki Toyama
发明人： Akihiko Takase , Masahiro Takatori , Masaru Murakami , Kaori Nakayama , Hitoshi Yajima , Takaaki Toyama
IPC分类号： H04J3/04 , H04L12/28 , H04L12/951 , H04Q3/00 , H04Q11/04 , H04L12/56
CPC分类号： H04L12/5692 , H04L49/3081 , H04Q11/0478 , H04L2012/5658
摘要： For reducing the scale of a multiplexer, a lower speed ATM interface block, an interface block for SDT mode circuit emulation, and an interface block for UDT mode circuit emulation perform processing for terminating services provided by lower speed transmission lines accommodated therein, and part of AAL processing, which is pre-processing depending on a service, for generating ATM cells from signals received by a terminated service, and send the processed signal to a higher speed line interface using a previously assigned time slot on a time-division bus. The higher speed line interface once stores the signals received from the time-division bus in a buffer, and subsequently performs certain processing including a common portion for respective signals for generating therefrom ATM cells in which the signals are stored in payloads. The generated ATM cells are multiplexed and transmitted onto a higher speed transmission line.
摘要翻译：为了减少多路复用器的规模，低速ATM接口块，用于SDT模式电路仿真的接口块和用于UDT模式电路仿真的接口块执行用于终止由其中容纳的低速传输线提供的服务的处理，并且部分 AAL处理，其是根据服务进行的预处理，用于由终止的服务接收的信号产生ATM信元，并且使用时分总线上的先前分配的时隙将处理的信号发送到更高速线路接口。较高速度线路接口一次将从时分总线接收的信号存储在缓冲器中，并且随后执行包括用于从其生成的相应信号的公共部分的某些处理，其中信号被存储在有效载荷中的ATM信元。所生成的ATM信元被复用并发送到更高速的传输线上。

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