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41. 发明申请

US20100308454A1 POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD 有权
标题翻译：功率半导体器件封装和制造方法
公开(公告)号：US20100308454A1
公开(公告)日：2010-12-09
申请号：US12479995
申请日：2009-06-08
申请人： Jun Lu , Francois Hebert , Kai Liu , Xiaotian Zhang
发明人： Jun Lu , Francois Hebert , Kai Liu , Xiaotian Zhang
IPC分类号： H01L23/48 , H01L21/78
CPC分类号： H01L23/492 , H01L23/04 , H01L24/37 , H01L24/40 , H01L25/072 , H01L29/0657 , H01L2224/37011 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/73253 , H01L2224/84801 , H01L2224/8485 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/12044 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/83 , H01L2224/37099
摘要： A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.
摘要翻译：功率半导体器件封装包括导电组件，其包括连接结构和具有穿过其形成的孔的半导体管芯，所述孔的尺寸和构造为间隔地接收连接结构。在替代实施例中，功率半导体器件封装包括导电组件，该导电组件包括连接结构和设置在与之间隔开的连接结构的任一侧上的一对半导体管芯。

42. 发明申请

US20090057869A1 CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POWER CONVERSION 审中-公开
标题翻译：用于高效直流 - 直流电源转换的高压侧和低端NMOS管
公开(公告)号：US20090057869A1
公开(公告)日：2009-03-05
申请号：US11849160
申请日：2007-08-31
申请人： Francois Hebert , Xiaotian Zhang , Kai Liu , Ming Sun , Anup Bhalla
发明人： Francois Hebert , Xiaotian Zhang , Kai Liu , Ming Sun , Anup Bhalla
IPC分类号： H01L23/52
CPC分类号： H01L24/41 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/91 , H01L25/072 , H01L2224/0401 , H01L2224/04042 , H01L2224/05552 , H01L2224/05554 , H01L2224/0603 , H01L2224/16245 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45014 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49112 , H01L2224/49171 , H01L2224/73221 , H01L2224/73253 , H01L2224/73265 , H01L2224/83801 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01055 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2924/00015 , H01L2224/37099 , H01L2924/206
摘要： A circuit package assembly is disclosed. The assembly includes a conductive substrate; a high-side n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a source on a side facing a surface of the conductive substrate and in electrical contact therewith and a low-side standard n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a drain on a side facing the conductive substrate and in electrical contact therewith. Co-packaging of high-side and low-side NMOSFETs in this manner may reduce package size and parasitic inductance and capacitance compared to conventional packaging.
摘要翻译：公开了电路封装组件。组件包括导电基板; 具有在与导电基板的表面相对并与其电接触的一侧具有源极的高边n沟道金属氧化物半导体场效应晶体管（NMOSFET）和低侧标准n沟道金属氧化物半导体场效应晶体管（ NMOSFET），其在面向导电基板的一侧具有漏极并与其电接触。与传统封装相比，以这种方式共同封装高边和低边NMOSFET可以减小封装尺寸和寄生电感和电容。

43. 发明申请

US20060145312A1 Dual flat non-leaded semiconductor package 审中-公开
标题翻译：双平面无铅半导体封装
公开(公告)号：US20060145312A1
公开(公告)日：2006-07-06
申请号：US11029653
申请日：2005-01-05
申请人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
发明人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/49113 , H01L2224/49171 , H01L2224/4943 , H01L2224/85 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.
摘要翻译： DFN半导体封装包括引线框架，其具有与漏极引线，栅极引线和源极引线一体形成的管芯焊接焊盘，耦合到管芯焊接焊盘的管芯，耦合到源极引线的管芯源极接合区域和管芯栅极键合区域，以及密封剂，其至少部分地覆盖晶片，漏极引线，栅极引线和源极引线。

44. 发明申请

US20150206868A1 FLIP CHIP SEMICONDUCTOR DEVICE 有权
标题翻译： FLIP芯片半导体器件
公开(公告)号：US20150206868A1
公开(公告)日：2015-07-23
申请号：US14158830
申请日：2014-01-19
申请人： Xiaotian Zhang , Hamaz Yilmaz , Jun Lu , Xiaoguang Zeng , Ming-Chen Lu
发明人： Xiaotian Zhang , Hamaz Yilmaz , Jun Lu , Xiaoguang Zeng , Ming-Chen Lu
IPC分类号： H01L25/00 , H01L25/07 , H01L23/495 , H01L21/78 , H01L25/16
CPC分类号： H01L25/50 , H01L23/49503 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L23/49575 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L25/072 , H01L25/165 , H01L2224/0401 , H01L2224/04034 , H01L2224/04042 , H01L2224/05552 , H01L2224/05554 , H01L2224/0603 , H01L2224/06135 , H01L2224/16245 , H01L2224/29139 , H01L2224/32245 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/4103 , H01L2224/48091 , H01L2224/48137 , H01L2224/48195 , H01L2224/48247 , H01L2224/48257 , H01L2224/49112 , H01L2224/49113 , H01L2224/49171 , H01L2224/73221 , H01L2224/73253 , H01L2224/73263 , H01L2224/73265 , H01L2224/83805 , H01L2224/84801 , H01L2224/8485 , H01L2224/92157 , H01L2224/92225 , H01L2224/92246 , H01L2224/92247 , H01L2924/00014 , H01L2924/12042 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599
摘要： A semiconductor device package comprises a lead frame having a die paddle comprising a first chip installation area and a second chip installation area, a recess area formed in the first chip installation area, and multiple metal pillars formed in the recess area, a notch divides the first chip installation area into a transverse base extending transversely and a longitudinal base extending longitudinally, and separates the recess area into a transverse recess part formed in the transverse base and a longitudinal recess part formed in longitudinal base; a portion of a transverse extending part connecting to an external pin extends into a portion inside of the notch.
摘要翻译：一种半导体器件封装，包括具有包括第一芯片安装区域和第二芯片安装区域的模板的引线框架，形成在第一芯片安装区域中的凹部区域和形成在凹部区域中的多个金属柱，凹口将第一芯片安装区域横向延伸的横向基部和纵向延伸的纵向基部，并且将凹部区域分离成形成在横向基部中的横向凹部和形成在纵向基部中的纵向凹部; 连接到外部销的横向延伸部分的一部分延伸到凹口内部的一部分。

45. 发明申请

US20150035129A1 STACKED MULTI - CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：堆叠多芯片包装结构及其制造方法
公开(公告)号：US20150035129A1
公开(公告)日：2015-02-05
申请号：US13955206
申请日：2013-07-31
申请人： Xiaotian Zhang , Hua Pan , Ming-Chen Lu , Jun Lu , Hamza Yilmaz
发明人： Xiaotian Zhang , Hua Pan , Ming-Chen Lu , Jun Lu , Hamza Yilmaz
IPC分类号： H01L23/495 , H01L23/00
CPC分类号： H01L25/50 , H01L21/304 , H01L21/56 , H01L21/78 , H01L22/14 , H01L23/3675 , H01L23/4334 , H01L23/492 , H01L23/49503 , H01L23/49524 , H01L23/49534 , H01L23/49562 , H01L23/49575 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/27 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0652 , H01L25/07 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/118 , H01L2224/13022 , H01L2224/32245 , H01L2224/37013 , H01L2224/37147 , H01L2224/40095 , H01L2224/40137 , H01L2224/40145 , H01L2224/40245 , H01L2224/40247 , H01L2224/48091 , H01L2224/48106 , H01L2224/48145 , H01L2224/48177 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/49113 , H01L2224/49171 , H01L2224/73263 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/83851 , H01L2224/84801 , H01L2224/85 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06572 , H01L2225/06589 , H01L2924/00014 , H01L2924/07802 , H01L2924/0781 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.
摘要翻译：堆叠多芯片封装结构包括引线框架，安装在引线框架上的第一半导体芯片，安装在引线框架上的第二半导体芯片翻转芯片，安装在第一和第二半导体芯片顶部的金属夹子和第三个半导体芯片堆叠在餐夹上; 将第三半导体芯片上的电极电连接到第一和第二半导体芯片和引线框架的引脚的接合线; 塑料成型封装引线框架，芯片和金属夹。

46. 发明授权

US08484318B2 Method, apparatus and system for upgrading through multicast 有权
标题翻译：通过组播升级的方法，设备和系统
公开(公告)号：US08484318B2
公开(公告)日：2013-07-09
申请号：US13052566
申请日：2011-03-21
申请人： Xiaotian Zhang , Junxia Xu
发明人： Xiaotian Zhang , Junxia Xu
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L12/1895 , H04L41/04 , H04L41/082
摘要： A method for upgrading a device through multicast is disclosed. The method includes: monitoring a common channel of a multicast server, where information about all subfiles of a current packaged mirror file is multicast in the common channel; obtaining information about a subfile required for upgrading the device from packets in the common channel, where the information includes an address of a subchannel that bears the subfile on the multicast server; and switching to the subchannel according to the address of the subchannel that bears the subfile required for upgrade, receiving the subfile multicast in the subchannel, and validating the subfile. Further, an apparatus and system for upgrading a device through multicast are disclosed. The technical solution under the present invention can upgrade both a single-system or single-module device and a multi-system or multi-module device through multicast, the time required for upgrading the devices is reduced, and the upgrade status of the devices can be tracked in real time.
摘要翻译：公开了一种通过组播升级设备的方法。该方法包括：监视多播服务器的公共信道，其中当前打包的镜像文件的所有子文件的信息在公共信道中进行多播; 获取关于从所述公共信道的数据包升级所述设备所需的子文件的信息，其中所述信息包括在所述多播服务器上承载所述子文件的子信道的地址; 根据承载升级所需子文件的子信道的地址切换到子信道，接收子信道中的子文件多播，并验证子文件。此外，公开了一种通过多播来升级设备的装置和系统。本发明的技术方案可以通过组播来升级单系统或单模块设备，多系统或多模块设备，降低设备升级所需的时间，设备的升级状态可以被实时追踪。

47. 发明申请

US20120322207A1 SEMICONDUCTOR PACKAGE WITH ADHESIVE MATERIAL PRE-PRINTED ON THE LEAD FRAME AND CHIP, AND ITS MANUFACTURING METHOD 有权
标题翻译：在铅框架和芯片上预先印刷的粘合材料的半导体封装及其制造方法
公开(公告)号：US20120322207A1
公开(公告)日：2012-12-20
申请号：US13545225
申请日：2012-07-10
申请人： Xiaotian Zhang , Jun Lu
发明人： Xiaotian Zhang , Jun Lu
IPC分类号： H01L21/60
CPC分类号： H01L24/37 , H01L23/3107 , H01L23/49513 , H01L23/4952 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/27 , H01L24/29 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L24/84 , H01L2224/04042 , H01L2224/05 , H01L2224/0603 , H01L2224/2919 , H01L2224/32245 , H01L2224/371 , H01L2224/40245 , H01L2224/4103 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49111 , H01L2224/73221 , H01L2224/73265 , H01L2224/83192 , H01L2224/83855 , H01L2224/83856 , H01L2224/8585 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2224/83 , H01L2224/84 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.
摘要翻译：本发明公开了一种半导体封装，其具有预先印刷在引线框架和芯片上的粘合剂材料及其制造方法。粘合剂材料通过预打印被施加到芯片载体和引线框架的引脚以及半导体芯片的前电极上。半导体芯片的背面粘附在芯片载体上，并且半导体芯片的前电极和引脚分别与金属连接器连接。根据不同的应用要求，根据半导体芯片和金属连接器的接触区域的尺寸和形状来施加粘合材料的尺寸，形状和厚度。特别地，通过预先印刷粘合剂材料形成粘合剂区域，从而显着提高半导体产品的质量和性能，并提高生产率。

48. 发明申请

US20110278709A1 STACKED-DIE PACKAGE FOR BATTERY POWER MANAGEMENT 有权
标题翻译：电池电源管理的堆叠式封装
公开(公告)号：US20110278709A1
公开(公告)日：2011-11-17
申请号：US13089065
申请日：2011-04-18
申请人： Jun Lu , Allen Chang , Xiaotian Zhang
发明人： Jun Lu , Allen Chang , Xiaotian Zhang
IPC分类号： H01L23/495
CPC分类号： H01L21/823487 , H01L23/4952 , H01L23/49524 , H01L23/49531 , H01L23/49562 , H01L23/49575 , H01L23/58 , H01L24/37 , H01L24/39 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/91 , H01L25/071 , H01L25/074 , H01L25/18 , H01L27/088 , H01L2224/05552 , H01L2224/0603 , H01L2224/32145 , H01L2224/32245 , H01L2224/37124 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49112 , H01L2224/4917 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H02J7/0031 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A battery protection package assembly is disclosed. The assembly includes a power control integrated circuit (IC) with pins for a supply voltage input (VCC) and a ground (VSS) on a first side of the power control IC. First and second common-drain metal oxide semiconductor field effect transistors (MOSFETs) are electrically coupled to the power control IC. The power control IC and the first and second common-drain metal oxide semiconductor field effect transistors (MOSFET) are co-packaged on a common die pad. The power control IC is vertically stacked on top of one or more of the first and second common-drain MOSFETs. Leads coupled to a supply voltage input (VCC) and a ground (VSS) of the power control IC are on a first side of the common die pad.
摘要翻译：公开了一种电池保护封装组件。该组件包括功率控制集成电路（IC），其具有用于功率控制IC的第一侧上的电源电压输入（VCC）和接地（VSS）的引脚。第一和第二共漏极金属氧化物半导体场效应晶体管（MOSFET）电耦合到功率控制IC。功率控制IC和第一和第二共漏极金属氧化物半导体场效应晶体管（MOSFET）共同封装在公共管芯焊盘上。功率控制IC垂直堆叠在第一和第二共漏极MOSFET中的一个或多个的顶部上。耦合到功率控制IC的电源电压输入（VCC）和接地（VSS）的引线位于公共管芯焊盘的第一侧上。

49. 发明授权

US07951651B2 Dual flat non-leaded semiconductor package 有权
标题翻译：双平面无铅半导体封装
公开(公告)号：US07951651B2
公开(公告)日：2011-05-31
申请号：US12474089
申请日：2009-05-28
申请人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
发明人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
IPC分类号： H01L21/00
CPC分类号： H01L24/48 , H01L23/3107 , H01L23/4952 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/45 , H01L24/49 , H01L24/83 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/05599 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48799 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/0665 , H01L2924/00012
摘要： A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.
摘要翻译： DFN半导体封装包括引线框架，其具有与漏极引线，栅极引线和源极引线一体形成的管芯焊接焊盘，耦合到管芯焊接焊盘的管芯，耦合到源极引线的管芯源极接合区域和管芯栅极键合区域，以及密封剂，其至少部分地覆盖晶片，漏极引线，栅极引线和源极引线。

50. 发明授权

US07612439B2 Semiconductor package having improved thermal performance 有权
标题翻译：具有改善的热性能的半导体封装
公开(公告)号：US07612439B2
公开(公告)日：2009-11-03
申请号：US11316614
申请日：2005-12-22
申请人： Xiaotian Zhang , Argo Chang , James Lee , Ryan Huang , Kai Liu , Ming Sun
发明人： Xiaotian Zhang , Argo Chang , James Lee , Ryan Huang , Kai Liu , Ming Sun
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L23/49575 , H01L23/49562 , H01L24/48 , H01L24/49 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die bonding pad, a plurality of first leads coupled to the first die bonding pad, a plurality of second leads coupled to the second die bonding pad, and an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads. The package may be a TSSOP-8 composite package having a common drain MOSFET pair and an IC.
摘要翻译：公开了一种复合半导体封装。封装包括具有第一和第二裸片接合焊盘的引线框架，第一和第二管芯接合焊盘之间具有大的横向间隔，接合到第一管芯接合焊盘的第一器件，与第二管芯接合焊盘接合的第二器件，耦合到第一裸片焊接焊盘的多个第一引线，耦合到第二管芯焊盘的多个第二引线以及覆盖引线框架的密封剂，第一和第二器件以及第一和第二多个元件的至少一部分的领导。该封装可以是具有公共漏极MOSFET对和IC的TSSOP-8复合封装。

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