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1. 发明申请

US20090057869A1 CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POWER CONVERSION 审中-公开
标题翻译：用于高效直流 - 直流电源转换的高压侧和低端NMOS管
公开(公告)号：US20090057869A1
公开(公告)日：2009-03-05
申请号：US11849160
申请日：2007-08-31
申请人： Francois Hebert , Xiaotian Zhang , Kai Liu , Ming Sun , Anup Bhalla
发明人： Francois Hebert , Xiaotian Zhang , Kai Liu , Ming Sun , Anup Bhalla
IPC分类号： H01L23/52
CPC分类号： H01L24/41 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/91 , H01L25/072 , H01L2224/0401 , H01L2224/04042 , H01L2224/05552 , H01L2224/05554 , H01L2224/0603 , H01L2224/16245 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45014 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49112 , H01L2224/49171 , H01L2224/73221 , H01L2224/73253 , H01L2224/73265 , H01L2224/83801 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01055 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2924/00015 , H01L2224/37099 , H01L2924/206
摘要： A circuit package assembly is disclosed. The assembly includes a conductive substrate; a high-side n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a source on a side facing a surface of the conductive substrate and in electrical contact therewith and a low-side standard n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a drain on a side facing the conductive substrate and in electrical contact therewith. Co-packaging of high-side and low-side NMOSFETs in this manner may reduce package size and parasitic inductance and capacitance compared to conventional packaging.
摘要翻译：公开了电路封装组件。组件包括导电基板; 具有在与导电基板的表面相对并与其电接触的一侧具有源极的高边n沟道金属氧化物半导体场效应晶体管（NMOSFET）和低侧标准n沟道金属氧化物半导体场效应晶体管（ NMOSFET），其在面向导电基板的一侧具有漏极并与其电接触。与传统封装相比，以这种方式共同封装高边和低边NMOSFET可以减小封装尺寸和寄生电感和电容。

2. 发明申请

US20090108456A1 Solder-top Enhanced Semiconductor Device and Method for Low Parasitic Impedance Packaging 有权
标题翻译：焊接增强型半导体器件和低寄生阻抗封装方法
公开(公告)号：US20090108456A1
公开(公告)日：2009-04-30
申请号：US11932845
申请日：2007-10-31
申请人： Francois Hebert , Anup Bhalla , Kai Liu , Ming Sun
发明人： Francois Hebert , Anup Bhalla , Kai Liu , Ming Sun
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L24/40 , H01L23/4952 , H01L23/49562 , H01L23/64 , H01L24/29 , H01L24/33 , H01L24/37 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L2224/05624 , H01L2224/29101 , H01L2224/29111 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40249 , H01L2224/4103 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/83194 , H01L2224/83801 , H01L2224/84801 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/157 , H01L2924/181 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/29099 , H01L2224/37099
摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.
摘要翻译：提出了一种焊顶增强型半导体器件进行封装。焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。至少一个接触区域电连接到至少一个接触增强区域。每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。用于制造焊料顶部器件的方法包括：a）将顶部金属层的光刻图案化成接触区域和接触增强区域。 b）使用用于增加复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

3. 发明申请

US20100308454A1 POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD 有权
标题翻译：功率半导体器件封装和制造方法
公开(公告)号：US20100308454A1
公开(公告)日：2010-12-09
申请号：US12479995
申请日：2009-06-08
申请人： Jun Lu , Francois Hebert , Kai Liu , Xiaotian Zhang
发明人： Jun Lu , Francois Hebert , Kai Liu , Xiaotian Zhang
IPC分类号： H01L23/48 , H01L21/78
CPC分类号： H01L23/492 , H01L23/04 , H01L24/37 , H01L24/40 , H01L25/072 , H01L29/0657 , H01L2224/37011 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/73253 , H01L2224/84801 , H01L2224/8485 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/12044 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/83 , H01L2224/37099
摘要： A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.
摘要翻译：功率半导体器件封装包括导电组件，其包括连接结构和具有穿过其形成的孔的半导体管芯，所述孔的尺寸和构造为间隔地接收连接结构。在替代实施例中，功率半导体器件封装包括导电组件，该导电组件包括连接结构和设置在与之间隔开的连接结构的任一侧上的一对半导体管芯。

4. 发明申请

US20090167477A1 Compact Inductive Power Electronics Package 有权
标题翻译：紧凑型感应电力电子封装
公开(公告)号：US20090167477A1
公开(公告)日：2009-07-02
申请号：US12397473
申请日：2009-03-04
申请人： Tao Feng , Xiaotian Zhang , Francois Hebert , Ming Sun
发明人： Tao Feng , Xiaotian Zhang , Francois Hebert , Ming Sun
IPC分类号： H01F5/00 , H01F41/00
CPC分类号： H01L23/495 , H01F3/14 , H01F17/0033 , H01F17/062 , H01F27/2828 , H01F2027/2814 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/00014 , H01L2924/01019 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , Y10T29/49073 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： An inductive power electronics package is disclosed. It has a circuit substrate with power inductor attached atop. The power inductor has inductor core of closed magnetic loop with an interior window. The closed magnetic loop can include air gap for inductance adjustment. The circuit substrate has bottom half-coil forming elements constituting a bottom half-coil beneath the inductor core. Also provided are top half-coil forming elements interconnected with the bottom half-coil forming elements to form an inductive coil enclosing the inductor core. An inner connection chip can be added in the interior window for interconnecting bottom half-coil forming elements with top half-coil forming elements. An outer connection chip can be added about the inductor core for interconnecting bottom half-coil forming elements with top half-coil forming elements outside the inductor core. A power Integrated Circuit can be attached to the top side of the circuit substrate as well.
摘要翻译：公开了感应电力电子封装。它有一个电路基板，带有功率电感器。功率电感器具有具有内部窗口的闭合磁环的电感器芯。封闭的磁环可以包括用于电感调节的气隙。电路基板具有构成电感器芯下方的下半线圈的底部半线圈形成元件。还提供了与底部半线圈形成元件互连以形成包围电感器芯的感应线圈的顶部半线圈形成元件。内部连接芯片可以添加到内部窗口中，用于将底部半线圈形成元件与顶部半线圈形成元件相互连接。外部连接芯片可以围绕电感器芯添加，用于将底部半线圈形成元件与电感器芯外部的顶部半线圈形成元件互连。功率集成电路也可以连接到电路基板的顶侧。

5. 发明授权

US08053298B2 Planar split-gate high-performance MOSFET structure and manufacturing method 有权
标题翻译：平面分闸高性能MOSFET结构及制造方法
公开(公告)号：US08053298B2
公开(公告)日：2011-11-08
申请号：US12381813
申请日：2009-03-16
申请人： Anup Bhalla , Francois Hebert , Daniel S. Ng
发明人： Anup Bhalla , Francois Hebert , Daniel S. Ng
IPC分类号： H01L21/337
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/66712 , H01L29/7828
摘要： This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.
摘要翻译：本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻设备。晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区。

6. 发明申请

US20090218620A1 High power and high temperature semiconductor power devices protected by non-uniform ballasted sources 有权
标题翻译：由不均匀的压载源保护的大功率和高温半导体功率器件
公开(公告)号：US20090218620A1
公开(公告)日：2009-09-03
申请号：US12074087
申请日：2008-02-28
申请人： Francois Hebert , Anup Bhalla
发明人： Francois Hebert , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/7802 , H01L24/05 , H01L29/0696 , H01L29/086 , H01L29/41741 , H01L29/41775 , H01L29/456 , H01L29/7803 , H01L2224/0603 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers.
摘要翻译：本发明公开了一种半导体功率器件，其设置在支撑外延层的半导体衬底上，作为由外延层构成的漂移区。半导体功率器件还包括超结结构，其包括设置在多个外延层中的多个掺杂侧壁。外延层具有多个沟槽，其中多个外延层开放并填充，其中掺杂的列沿着设置在多个外延层中的沟槽的侧壁设置。

7. 发明申请

US20080067584A1 Inverted-trench grounded-source FET structure with trenched source body short electrode 有权
标题翻译：反沟槽接地源FET结构，具有沟槽源体短路电极
公开(公告)号：US20080067584A1
公开(公告)日：2008-03-20
申请号：US11522669
申请日：2006-09-17
申请人： Sik K Lui , Francois Hebert , Anup Bhalla
发明人： Sik K Lui , Francois Hebert , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/781 , H01L21/823487 , H01L27/088 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.
摘要翻译：本发明公开了底源横向扩散MOS（BS-LDMOS）器件。器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉陷通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体用于将主体区域和源区域电连接到用作源电极的衬底的底部。漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

8. 发明申请

US20080006951A1 Copper bonding compatible bond pad structure and method 有权
标题翻译：铜键合兼容键合焊盘结构及方法
公开(公告)号：US20080006951A1
公开(公告)日：2008-01-10
申请号：US11444977
申请日：2006-05-31
申请人： Francois Hebert , Anup Bhalla
发明人： Francois Hebert , Anup Bhalla
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05017 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05556 , H01L2224/05624 , H01L2224/0603 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/85201 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.
摘要翻译：公开了一种铜键合兼容的键合焊盘结构及其相关方法。器件接合焊盘结构包括由互连金属的区域和非导电钝化材料的区域形成的缓冲结构，该缓冲结构为器件的下层和结构提供缓冲。

9. 发明申请

US20100024213A1 COPPER BONDING METHOD 有权
标题翻译：铜接合方法
公开(公告)号：US20100024213A1
公开(公告)日：2010-02-04
申请号：US12541881
申请日：2009-08-14
申请人： Francois Hebert , Anup Bhalla
发明人： Francois Hebert , Anup Bhalla
IPC分类号： H01R43/02
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05017 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05556 , H01L2224/05624 , H01L2224/0603 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/85201 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.
摘要翻译：公开了一种铜键合兼容的键合焊盘结构及其相关方法。器件接合焊盘结构包括由互连金属的区域和非导电钝化材料的区域形成的缓冲结构，该缓冲结构为器件的下层和结构提供缓冲。

10. 发明申请

US20090242973A1 SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON 审中-公开
标题翻译：使用POLYSILICON的TRENCH-DMOS器件的源和体接触结构
公开(公告)号：US20090242973A1
公开(公告)日：2009-10-01
申请号：US12060096
申请日：2008-03-31
申请人： Francois Hebert , Anup Bhalla
发明人： Francois Hebert , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/086 , H01L29/0869 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed.
摘要翻译：半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物沿着源区域的侧壁和氧化物的侧壁设置。还公开了制造这种装置的方法。

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