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41. 发明授权

US07361563B2 Methods of fabricating a semiconductor device using a selective epitaxial growth technique 有权
标题翻译：使用选择性外延生长技术制造半导体器件的方法
公开(公告)号：US07361563B2
公开(公告)日：2008-04-22
申请号：US11299447
申请日：2005-12-09
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/205 , H01L29/80 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.
摘要翻译：使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。将具有凹部的基板装入反应室。将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

42. 发明申请

US20080079458A1 Impedance-controlled pseudo-open drain output driver circuit and method for driving the same 失效
标题翻译：阻抗控制的开漏输出驱动电路及其驱动方法
公开(公告)号：US20080079458A1
公开(公告)日：2008-04-03
申请号：US11906365
申请日：2007-10-01
申请人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
发明人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
IPC分类号： H03K19/0185
CPC分类号： H03K19/00384
摘要： An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.
摘要翻译：阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有一个预期的阻抗。

43. 发明申请

US20080073713A1 Method of fabricating semiconductor device having stress enhanced MOS transistor and semiconductor device fabricated thereby 审中-公开
标题翻译：制造具有应力增强型MOS晶体管的半导体器件及其制造的半导体器件的方法
公开(公告)号：US20080073713A1
公开(公告)日：2008-03-27
申请号：US11785994
申请日：2007-04-23
申请人： Ki-Chul Kim , Dong-Suk Shin
发明人： Ki-Chul Kim , Dong-Suk Shin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of fabricating a semiconductor device having a stress enhanced MOS transistor is provided. A MOS transistor may be formed in a desired, or alternatively, a predetermined region of a semiconductor substrate. A first sacrificial pattern, formed over the source and drain regions of a MOS transistor, may expose sidewall spacers and cover the upper region of the gate pattern. Thinner spacers may be formed by etching the exposed sidewall spacers using the first sacrificial pattern as an etch mask. A stress liner may be formed over the MOS transistor having the thinner spacers.
摘要翻译：提供一种制造具有应力增强型MOS晶体管的半导体器件的方法。 MOS晶体管可以形成在半导体衬底的期望或替代地预定区域中。形成在MOS晶体管的源极和漏极区域上的第一牺牲图案可以暴露侧壁间隔物并覆盖栅极图案的上部区域。可以通过使用第一牺牲图案作为蚀刻掩模蚀刻暴露的侧壁间隔物来形成更薄的间隔物。可以在具有较薄间隔物的MOS晶体管上形成应力衬垫。

44. 发明授权

US07307274B2 Transistors having reinforcement layer patterns and methods of forming the same 有权
标题翻译：具有加强层图案的晶体管及其形成方法
公开(公告)号：US07307274B2
公开(公告)日：2007-12-11
申请号：US11204564
申请日：2005-08-15
申请人： Ho Lee , Dong-Suk Shin , Hwa-Sung Rhee , Ueno Tetsuji , Seung-Hwan Lee
发明人： Ho Lee , Dong-Suk Shin , Hwa-Sung Rhee , Ueno Tetsuji , Seung-Hwan Lee
IPC分类号： H01L29/06
CPC分类号： H01L29/66628 , H01L21/26586 , H01L29/1054 , H01L29/6659 , H01L29/66651 , H01L29/7834
摘要： According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To the end, at least one gate pattern is disposed on an active region of a semiconductor substrate. Reinforcement layer patterns are formed to extend respectively from sidewalls of the gate pattern and disposed on a main surface of the semiconductor substrate. Each reinforcement layer pattern partially exposes each sidewall of the gate pattern. Impurity regions are disposed in the reinforcement layer patterns and the active region of the semiconductor substrate and overlap the gate pattern. Spacer patterns are disposed on the reinforcement layer patterns and partially cover the sidewalls of the gate pattern.
摘要翻译：根据本发明的一些实施例，提供了包括具有加强层图案的晶体管和其形成方法的线光掩模。晶体管和方法提供了在半导体制造工艺期间补偿部分去除量的应变硅层的方法。最后，在半导体衬底的有源区上设置至少一个栅极图案。加强层图案分别形成为从栅极图案的侧壁延伸并设置在半导体衬底的主表面上。每个加强层图案部分地暴露栅极图案的每个侧壁。杂质区域设置在加强层图案和半导体衬底的有源区域中并与栅极图案重叠。间隔图案设置在加强层图案上并且部分覆盖栅极图案的侧壁。

45. 发明申请

US20060148154A1 Semiconductor devices having faceted channels and methods of fabricating such devices 有权
标题翻译：具有小平面通道的半导体器件和制造这种器件的方法
公开(公告)号：US20060148154A1
公开(公告)日：2006-07-06
申请号：US11281599
申请日：2005-11-18
申请人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
发明人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L29/045 , H01L29/66795 , H01L29/7851 , H01L29/7853
摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.
摘要翻译：公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

46. 发明申请

US20050279997A1 Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same 有权
标题翻译：在使用其制造的单晶半导体和半导体器件上选择性地形成外延半导体层的方法
公开(公告)号：US20050279997A1
公开(公告)日：2005-12-22
申请号：US11154236
申请日：2005-06-16
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/20 , H01L21/205 , H01L21/28 , H01L21/336 , H01L29/772
CPC分类号： H01L21/28044 , H01L21/02378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/66628 , H01L29/66772
摘要： In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.
摘要翻译：在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中，单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶半导体图案，分别使用主半导体源气体和主蚀刻气体。使用选择性蚀刻气体去除非单晶外延半导体层。主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

47. 发明授权

US09431478B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09431478B2
公开(公告)日：2016-08-30
申请号：US14600142
申请日：2015-01-20
申请人： Yeong-Jong Jeong , Jeong-Yun Lee , Geo-Myung Shin , Dong-Suk Shin , Si-Hyung Lee , Seo-Jin Jeong
发明人： Yeong-Jong Jeong , Jeong-Yun Lee , Geo-Myung Shin , Dong-Suk Shin , Si-Hyung Lee , Seo-Jin Jeong
IPC分类号： H01L27/088 , H01L29/06 , H01L29/78 , B82Y10/00 , H01L29/775 , H01L29/41
CPC分类号： H01L29/7848 , B82Y10/00 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0924 , H01L29/06 , H01L29/0653 , H01L29/0673 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/413 , H01L29/42392 , H01L29/775 , H01L29/78 , H01L29/7851 , H01L29/7853 , H01L29/78696
摘要： A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.
摘要翻译：一种半导体器件包括由场绝缘层限定并沿着第一方向延伸的第一多沟道有源图案，该第一多沟道有源图案包括第一部分，该第一部分具有在向上方向上进一步向上方突出的顶表面，所述场绝缘层和所述第一部分的两侧上的第二部分，所述第二部分具有连续轮廓的侧壁和在所述场绝缘层的顶表面上向上方向突出的顶表面，并且在向上方向上突出小于第一部分的顶表面的第一部分上的栅电极，在第一多通道有源图案的第一部分上并且沿着不同于第一方向的第二方向延伸的栅电极，以及在第一部分的第二部分上的第一源极/漏极区域第一多通道有源图案并接触场绝缘层。

48. 发明申请

US20160148930A1 SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME 审中-公开
公开(公告)号：US20160148930A1
公开(公告)日：2016-05-26
申请号：US15009276
申请日：2016-01-28
申请人： Dong-Suk Shin , Hyun-Chul Kang , Dong-Hyun Roh , Pan-Kwi Park , Geo-Myung Shin , Nae-In Lee , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim
发明人： Dong-Suk Shin , Hyun-Chul Kang , Dong-Hyun Roh , Pan-Kwi Park , Geo-Myung Shin , Nae-In Lee , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim
IPC分类号： H01L27/088 , H01L29/10 , H01L27/02 , H01L29/165 , H01L29/78
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823425 , H01L27/0207 , H01L27/088 , H01L29/0847 , H01L29/1095 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/4966 , H01L29/66492 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7836
摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

49. 发明授权

US08748299B2 Semiconductor devices having an epitaxial layer on active regions and shallow trench isolation regions 有权
标题翻译：具有在有源区上的外延层和浅沟槽隔离区的半导体器件
公开(公告)号：US08748299B2
公开(公告)日：2014-06-10
申请号：US12656752
申请日：2010-02-16
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H01L21/36 , H01L21/20
CPC分类号： H01L29/6656 , H01L21/76232 , H01L29/665 , H01L29/66651 , H01L29/78
摘要： A semiconductor device includes an isolation layer pattern, an epitaxial layer pattern, a gate insulation layer pattern and a gate electrode. The isolation layer pattern is formed on a substrate, and defines an active region in the substrate. The isolation layer pattern extends in a second direction. The epitaxial layer pattern is formed on the active region and the isolation layer pattern, and has a width larger than that of the active region in a first direction perpendicular to the second direction. The gate insulation layer pattern is formed on the epitaxial layer pattern. The gate electrode is formed on the gate insulation layer pattern.
摘要翻译：半导体器件包括隔离层图案，外延层图案，栅极绝缘层图案和栅电极。隔离层图案形成在衬底上，并且在衬底中限定有源区。隔离层图案沿第二方向延伸。外延层图案形成在有源区和隔离层图案上，并且在垂直于第二方向的第一方向上具有大于有源区的宽度的宽度。栅极绝缘层图案形成在外延层图案上。栅电极形成在栅极绝缘层图案上。

50. 发明申请

US20120223364A1 TRANSISTORS AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US20120223364A1
公开(公告)日：2012-09-06
申请号：US13410475
申请日：2012-03-02
申请人： Hoi-Sung CHUNG , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
发明人： Hoi-Sung CHUNG , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/30608 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.
摘要翻译：在制造晶体管的方法中，在包括硅的衬底上形成栅极结构。蚀刻与栅极结构相邻的衬底的上部，以在衬底中形成第一凹部。在第一凹部中形成包括硅 - 锗的初步的第一外延层。蚀刻初步第一外延层的上部以在初步第一外延层上形成第二凹槽。此外，蚀刻与第二凹槽相邻的初步第一外延层的一部分，从而将初步第一外延层转变为第一外延层。在位于第一外延层上的第二凹槽中形成包括硅 - 锗的第二外延层。

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