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1. 发明授权

US07791377B2 Hierarchical time to digital converter 有权
标题翻译：数字转换器的分层时间
公开(公告)号：US07791377B2
公开(公告)日：2010-09-07
申请号：US12033782
申请日：2008-02-19
申请人： Chulwoo Kim , Minyoung Song , Sunghoon Ahn
发明人： Chulwoo Kim , Minyoung Song , Sunghoon Ahn
IPC分类号： G01R29/00 , H03D3/00 , H03D9/00
CPC分类号： H03K5/159 , G04F10/06 , H03K2005/00286
摘要： A time to digital converter having a hierarchical structure is provided. The time to digital converter includes: a plurality of delay stages for sequentially delaying a first signal for a specific delay time; a plurality of flip-flops for comparing delay signals of the first signal delayed by the delay stages with a second signal, and generating different outputs before and after a phase difference between the delay signals of the first signal and the second signal becomes smaller than a resolution of the phase detector; a selection signal generator for generating a selection signal for selecting a signal most similar to the second signal among the delay signals of the first signal from the outputs of the flip-flops; and a Multiplexer (MUX) for receiving the delay signals of the first signal and the selection signal, and outputting the signal most similar to the second signal among the delay signals of the first signal.
摘要翻译：提供具有层次结构的时间到数字转换器。数字转换器的时间包括：多个延迟级，用于在特定延迟时间内顺序地延迟第一信号; 多个触发器，用于将由延迟级延迟的第一信号的延迟信号与第二信号进行比较，并且在第一信号和第二信号的延迟信号之间的相位差之前和之后产生不同的输出变得小于相位检测器的分辨率; 选择信号发生器，用于从所述触发器的输出产生用于从所述第一信号的延迟信号中选择与所述第二信号最相似的信号的选择信号; 以及用于接收第一信号和选择信号的延迟信号的多路复用器（MUX），并且在第一信号的延迟信号中输出与第二信号最相似的信号。

2. 发明授权

US07579861B2 Impedance-controlled pseudo-open drain output driver circuit and method for driving the same 失效
标题翻译：阻抗控制的开漏输出驱动电路及其驱动方法
公开(公告)号：US07579861B2
公开(公告)日：2009-08-25
申请号：US11906365
申请日：2007-10-01
申请人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
发明人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00384
摘要： An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.
摘要翻译：阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有一个预期的阻抗。

3. 发明申请

US20080079458A1 Impedance-controlled pseudo-open drain output driver circuit and method for driving the same 失效
标题翻译：阻抗控制的开漏输出驱动电路及其驱动方法
公开(公告)号：US20080079458A1
公开(公告)日：2008-04-03
申请号：US11906365
申请日：2007-10-01
申请人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
发明人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
IPC分类号： H03K19/0185
CPC分类号： H03K19/00384
摘要： An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.
摘要翻译：阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有一个预期的阻抗。

4. 发明授权

US09460937B2 Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages 有权
标题翻译：混合基板，包括其的半导体封装以及用于制造半导体封装的方法
公开(公告)号：US09460937B2
公开(公告)日：2016-10-04
申请号：US14451982
申请日：2014-08-05
申请人： Daewoo Son , Chulwoo Kim
发明人： Daewoo Son , Chulwoo Kim
IPC分类号： H01L21/00 , H01L21/56 , H01L23/36 , H01L23/498 , H01L21/48 , H01L23/31 , H01L23/48 , H01L23/00 , H05K3/46
CPC分类号： H01L25/50 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/76879 , H01L23/3128 , H01L23/36 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L24/03 , H01L24/09 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/13025 , H01L2224/16225 , H01L2224/16237 , H01L2224/16238 , H01L2224/32145 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06586 , H01L2924/00014 , H01L2924/12042 , H01L2924/12044 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H05K3/4614 , H05K3/4626 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.
摘要翻译：提供了一种混合基板，包括该混合基板的半导体封装以及该半导体封装的制造方法。混合基板可以包括绝缘层和有机层。绝缘层可以包括顶部，与顶部相对的底部，以及具有不同节距的导电图案。有机层可以连接到绝缘层的底部，并且可以包括连接到导电图案的电路图案。导电图案可以包括第一金属图案和第二导电图案。第一金属图案可以具有第一间距，并且可以设置在绝缘层的顶部。第二导电图案可以具有大于第一间距的第二间距，并且可以从第一金属图案延伸以通过绝缘层连接到电路图案。

5. 发明申请

US20080238563A1 APPARATUS AND METHOD FOR MEASUREMENT OF TEMPERATURE USING OSCILLATORS 有权
标题翻译：使用振荡器测量温度的装置和方法
公开(公告)号：US20080238563A1
公开(公告)日：2008-10-02
申请号：US12060479
申请日：2008-04-01
申请人： Chulwoo Kim , Janghoon Song , Gilwon Yoon , Sangdon Jung
发明人： Chulwoo Kim , Janghoon Song , Gilwon Yoon , Sangdon Jung
IPC分类号： H03L1/02 , G01K7/00
CPC分类号： G01K7/32
摘要： A temperature sensor includes: a first oscillator that generates a first frequency signal; a second oscillator that generates a second frequency signal; a multiplexer that selectively passes the first frequency signal and the second frequency signal; and a frequency-to-digital converter that converts a frequency difference between the first frequency signal and the second frequency signal into a digital code.
摘要翻译：温度传感器包括：产生第一频率信号的第一振荡器; 产生第二频率信号的第二振荡器; 选择性地通过第一频率信号和第二频率信号的多路复用器; 以及频率 - 数字转换器，其将第一频率信号和第二频率信号之间的频率差转换成数字码。

6. 发明申请

US20070069784A1 Open-loop slew-rate controlled output driver 有权
标题翻译：开环压摆率控制输出驱动器
公开(公告)号：US20070069784A1
公开(公告)日：2007-03-29
申请号：US11482684
申请日：2006-07-06
申请人： Dong-Suk Shin , In-Hwa Jung , Jin-Han Kim , Chulwoo Kim , Hyung-Dong Lee
发明人： Dong-Suk Shin , In-Hwa Jung , Jin-Han Kim , Chulwoo Kim , Hyung-Dong Lee
IPC分类号： H03K5/12
CPC分类号： H03K19/00384 , H03K17/163 , H03K17/6872 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A slew-rate controlled output driver for use in a semiconductor device includes a PVT variation detection unit having a delay line for receiving a reference clock in order to detect a delay amount variation of the delay line determined according to process, voltage and temperature (PVT) variation; a selection signal generation unit for generating a driving selection signal which corresponds to a detection signal generated by the PVT variation detection unit; and an output driving unit having a plurality of driver units controlled by an output data and the driving selection signal for driving an output terminal with a driving strength which corresponds to the PVT variation.
摘要翻译：用于半导体器件的转换速率控制输出驱动器包括具有用于接收参考时钟的延迟线的PVT变化检测单元，以便检测根据处理，电压和温度（PVT）确定的延迟线的延迟量变化）变异选择信号生成单元，用于产生对应于由PVT变化检测单元生成的检测信号的驱动选择信号; 以及输出驱动单元，其具有由输出数据控制的多个驱动器单元和用于以对应于PVT变化的驱动强度来驱动输出端子的驱动选择信号。

7. 发明授权

US06784707B2 Delay locked loop clock generator 失效
标题翻译：延时锁定环时钟发生器
公开(公告)号：US06784707B2
公开(公告)日：2004-08-31
申请号：US10192734
申请日：2002-07-10
申请人： Chulwoo Kim , Sung-Mo Kang
发明人： Chulwoo Kim , Sung-Mo Kang
IPC分类号： H03L706
CPC分类号： H03L7/10 , H03K2005/00026 , H03L7/0812 , H03L7/089 , H03L7/0891 , H03L7/16
摘要： A delay locked loop (DLL) clock generator circuit is provided for generating a clock signal Clk according to a pair of input signals to the circuit. One of the input signals is a reference signal, and the second input signal is a feedback signal of a voltage controlled delay line circuit. The DLL circuit includes a phase detector that can be reset to expand the locking range for detecting a phase difference between the reference signal and the feedback signal. Based on the detected phase difference, the phase detector provides an output signal that is further processed by the DLL circuit to generate a number of delayed signals to a frequency multiplier. Using the delayed signals, the frequency multiplier generates a frequency multiplied clock signal having a frequency that is a multiple of the frequency of the reference signal.
摘要翻译：提供延迟锁定环（DLL）时钟发生器电路，用于根据到电路的一对输入信号产生时钟信号Clk。输入信号之一是参考信号，第二输入信号是电压控制延迟线电路的反馈信号。 DLL电路包括可以复位的相位检测器，以扩大用于检测参考信号和反馈信号之间的相位差的锁定范围。基于检测到的相位差，相位检测器提供输出信号，该输出信号由DLL电路进一步处理以产生到倍频器的多个延迟信号。使用延迟信号，倍频器产生频率为参考信号频率的倍数的倍频时钟信号。

8. 发明授权

US06784694B2 CMOS sequential logic configuration for an edge triggered flip-flop 失效
标题翻译：用于边沿触发的触发器的CMOS顺序逻辑配置
公开(公告)号：US06784694B2
公开(公告)日：2004-08-31
申请号：US10125736
申请日：2002-04-18
申请人： Chulwoo Kim , Sung-Mo Kang
发明人： Chulwoo Kim , Sung-Mo Kang
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A CMOS sequential logic circuit for an edge triggered flip-flop to lower power consumption in very large scale integrated (VLSI) circuit designs is disclosed. The circuit includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS and NMOS transistors are matched and joined as a data-sampling front end and a data-transferring back end to provide an output based on an input signal fed to a pair of transistor gates. Outputs from the pair of transistor gates charge and discharge internal nodes which connect the data-sampling front end to the data-transferring back end. The internal nodes also include a first latch that connects to a first internal node, and a second latch that connects to a second internal node. The latches prevent a floating voltage state for each of the first and second internal nodes and reduce power consumption during flip-flop transitions.
摘要翻译：公开了一种用于边缘触发触发器的CMOS顺序逻辑电路，以便在大规模集成（VLSI）电路设计中降低功耗。该电路包括多个PMOS晶体管和多个NMOS晶体管。 PMOS和NMOS晶体管作为数据采样前端和数据传输后端进行匹配和连接，以提供基于馈送到一对晶体管栅极的输入信号的输出。来自一对晶体管栅极的输出将数据采样前端连接到数据传输后端的内部节点进行充电和放电。内部节点还包括连接到第一内部节点的第一锁存器和连接到第二内部节点的第二锁存器。锁存器防止第一和第二内部节点中的每一个的浮动电压状态，并且在触发器转换期间降低功耗。

9. 发明授权

US06624665B2 CMOS skewed static logic and method of synthesis 有权
公开(公告)号：US06624665B2
公开(公告)日：2003-09-23
申请号：US10141255
申请日：2002-05-08
申请人： Chulwoo Kim , Sung-Mo Kang
发明人： Chulwoo Kim , Sung-Mo Kang
IPC分类号： H03K1996
CPC分类号： H03K19/0963
摘要： A new CMOS skewed static logic gate is provided having a logic function circuit and a positive feedback or accelerator circuit. The skewed gate uses a plurality of transistors matched and joined as a plurality of separate gate inputs to form the logic function circuit and the accelerator circuit. The accelerator circuit, which connects to an output of the logic function circuit, provides acceleration to the evaluation performed by the logic function circuit. The logic function circuit includes an evaluation path connected to a set of output transistors that connect to transistors of the accelerator circuit. The evaluation path includes a stacked set of low threshold voltage (Vt) transistors, which have a lower Vt than the set of output transistors. The output transistors are configured to receive a first input signal to precharge an output of the CMOS skewed static logic gate prior to the skewed gate receiving a second input signal.

10. 发明授权

US08350158B2 Tape wiring substrates and packages including the same 有权
标题翻译：胶带接线基板和包装件
公开(公告)号：US08350158B2
公开(公告)日：2013-01-08
申请号：US12507551
申请日：2009-07-22
申请人： Yechung Chung , Chulwoo Kim , Eunseok Song , Kyoungsei Choi
发明人： Yechung Chung , Chulwoo Kim , Eunseok Song , Kyoungsei Choi
IPC分类号： H05K1/00
CPC分类号： H05K1/0216 , H01L23/4985 , H01L24/17 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H05K1/114 , H05K1/189 , H05K2201/093 , H05K2201/09318 , H05K2201/09663 , H05K2201/09772 , H05K2201/09781 , H05K2201/10674 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, the chip mounting area further including an inner area and a peripheral area, the film further including a lower surface, and vias penetrating the film, the vias being located in the inner area, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film. Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, a lower surface, and vias penetrating the film, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film, the vias being located outside of the chip mounting area. Example embodiments are directed to packages including tape wiring substrates.
摘要翻译：示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域的上表面的膜，所述芯片安装区域还包括内部区域和周边区域，所述膜还包括下表面，以及穿透所述膜的通孔，所述通孔位于所述内部区域中，所述膜的上表面上的上金属层连接到半导体芯片的电极凸块，并且在所述膜的下表面上的下金属层。示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域，下表面和通孔的通孔的上表面的膜，在膜的上表面上的上金属层，并连接到膜的电极凸块半导体芯片以及下部金属层，通孔位于芯片安装区域的外侧。示例性实施例涉及包括带布线基板的封装。

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