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41. 发明授权

US06394114B1 Method for stripping copper in damascene interconnects 失效
标题翻译：在大马士革互连中剥离铜的方法
公开(公告)号：US06394114B1
公开(公告)日：2002-05-28
申请号：US09442312
申请日：1999-11-22
申请人： Subhash Gupta , Simon Chooi , Paul Ho , Mei Sheng Zhou
发明人： Subhash Gupta , Simon Chooi , Paul Ho , Mei Sheng Zhou
IPC分类号： C23G114
CPC分类号： H01L21/32134 , C23F1/34 , H01L21/7684 , Y10S134/902
摘要： An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.
摘要翻译：描述了在制造集成电路中的便宜且安全的铜去除方法。通过包含铵盐，胺和水的化学混合物将铜剥离或除去。可以通过改变铵盐组分的浓度和混合物中的水量来控制铜汽提速率。还提供了一种用于剥离铜并除去铜污染物的新型化学混合物。用于除去或剥离铜的新型化学混合物包括铵盐，胺和水。例如，新型化学混合物可以包含比例为1:1:1的氟化铵，水和乙二胺。

42. 发明授权

US06284657B1 Non-metallic barrier formation for copper damascene type interconnects 有权
标题翻译：铜镶嵌型互连的非金属阻挡层形成
公开(公告)号：US06284657B1
公开(公告)日：2001-09-04
申请号：US09512379
申请日：2000-02-25
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L2144
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831
摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
摘要翻译：用于形成具有非金属屏障的双镶嵌型导电互连的方法，其保护所述互连免受氟周围的低k，氟化介电材料的氟扩散。该方法的一个实施例特别适用于在0.15微米级的微电子制造中形成这种互连。

43. 发明授权

US06132521A Cleaning metal surfaces with alkyldione peroxides 失效
标题翻译：用烷基二酮过氧化物清洗金属表面
公开(公告)号：US06132521A
公开(公告)日：2000-10-17
申请号：US467132
申请日：1999-12-20
申请人： Subhash Gupta , Simon Chooi , Mei Sheng Zhou , Paul Ho
发明人： Subhash Gupta , Simon Chooi , Mei Sheng Zhou , Paul Ho
IPC分类号： C11D3/20 , C11D3/39 , C23G5/032 , B08B3/04
CPC分类号： C11D3/2072 , C11D3/2003 , C11D3/2093 , C11D3/3945 , C23G5/032 , Y10S134/902
摘要： A method of cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware without corroding or damaging the equipment parts and surfaces in the event of wafer breakage and non-wafer breakage is described. A solution includes an alkyldione peroxide, a stabilizing agent, and alcohols is used to oxidize the metal and form soluble complexes which are removed by the cleaning solution. Also, a alkyldione peroxide solution for cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware in the event of wafer breakage and non-wafer breakage is provided.
摘要翻译：描述了从设备硬件表面清除元素铜，钴或镍的方法，而不会在晶片断裂和非晶片断裂的情况下腐蚀或损坏设备部件和表面。溶液包括烷基二酮过氧化物，稳定剂，醇用于氧化金属并形成由清洗溶液除去的可溶性络合物。此外，提供了在晶片断裂和非晶片断裂的情况下从设备硬件的表面清除元素铜，钴或镍的烷基二氧化碳过氧化物溶液。

44. 发明授权

US06358842B1 Method to form damascene interconnects with sidewall passivation to protect organic dielectrics 有权
标题翻译：形成具有侧壁钝化的镶嵌互连以保护有机电介质的方法
公开(公告)号：US06358842B1
公开(公告)日：2002-03-19
申请号：US09633770
申请日：2000-08-07
申请人： Mei-Sheng Zhou , Simon Chooi , Yi Xu
发明人： Mei-Sheng Zhou , Simon Chooi , Yi Xu
IPC分类号： H01L213205
CPC分类号： H01L21/76831 , H01L21/31138 , H01L21/76808
摘要： A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors. A copper layer is deposited overlying the capping layer and filling the via openings. The copper layer is polished down to complete the damascene interconnects in the manufacture of the integrated circuit device.
摘要翻译：已经实现了在集成电路器件的制造中形成镶嵌互连的新方法。镶嵌互连可以是单镶嵌或双镶嵌。提供铜导体覆盖在半导体衬底上。第一钝化层被提供在铜导体上。沉积在第一钝化层上的低介电常数层。沉积覆盖在低介电常数层上的可选的覆盖层。沉积在覆盖层上的光致抗蚀剂层。覆盖层和低介电常数层被蚀刻通过以形成通孔。同时剥离光致抗蚀剂层，同时使用含硫气体在通路孔的侧壁上形成侧壁钝化层。从而防止侧壁弯曲和通过中毒。蚀刻第一钝化层以暴露下面的铜导体。沉积覆盖覆盖层并填充通孔的铜层。铜层被抛光以在集成电路器件的制造中完成镶嵌互连。

45. 发明授权

US06165891A Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer 有权
标题翻译：使用碳氮化物，氮化硼或氮化硼钝化层，蚀刻停止层和/或覆盖层的具有降低的电容的镶嵌结构
公开(公告)号：US06165891A
公开(公告)日：2000-12-26
申请号：US435434
申请日：1999-11-22
申请人： Simon Chooi , Yi Xu , Mei Sheng Zhou
发明人： Simon Chooi , Yi Xu , Mei Sheng Zhou
IPC分类号： H01L21/311 , H01L21/318 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763 , G03C5/00 , H01L21/302 , H01L23/48
CPC分类号： H01L21/76835 , H01L21/31122 , H01L21/318 , H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by providing a semiconductor structure having a first conductive layer thereover. A passivation layer is formed on the first conductive layer. A first dielectric layer is formed over the passivation layer, and an etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer, and an optional cap layer can be formed over the second dielectric layer. The cap layer, the second dielectric layer, the etch stop layer, and the first dielectric layer are patterned to form a via opening stopping on said passivation layer and a trench opening stopping on the first conductive layer. A carbon nitride passivation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen atmosphere. A boron nitride passivation layer, etch stop layer, or cap layer can be formed by PECVD using B.sub.2 H.sub.6, ammonia, and nitrogen. A boron carbon nitride passivatation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen and B.sub.2 H.sub.6 atmosphere.
摘要翻译：通过使用包含碳氮化物，氮化硼或碳氮化硼的低介电常数材料通过形成钝化层，蚀刻停止层和盖层中的一个或多个来形成具有降低的电容的镶嵌结构的方法和结构。该方法开始于提供其上具有第一导电层的半导体结构。在第一导电层上形成钝化层。第一电介质层形成在钝化层之上，并且在第一介电层上形成蚀刻停止层。第二介电层形成在蚀刻停止层上方，并且可以在第二介电层上形成任选的盖层。图案化盖层，第二电介质层，蚀刻停止层和第一介电层，以形成在所述钝化层上停止的通孔开口和在第一导电层上停止的沟槽开口。碳氮化物钝化层，蚀刻停止层或盖层可以通过在氮气气氛中的石墨靶磁控溅射来形成。可以通过使用B2H6，氨和氮的PECVD形成氮化硼钝化层，蚀刻停止层或盖层。硼氮化物钝化层，蚀刻停止层或盖层可以通过在氮气和B2H6气氛中的石墨靶的磁控溅射形成。

46. 发明授权

US06436824B1 Low dielectric constant materials for copper damascene 有权
标题翻译：用于铜镶嵌的低介电常数材料
公开(公告)号：US06436824B1
公开(公告)日：2002-08-20
申请号：US09346526
申请日：1999-07-02
申请人： Simon Chooi , Mei Sheng Zhou , Yi Xu
发明人： Simon Chooi , Mei Sheng Zhou , Yi Xu
IPC分类号： H01L2144
CPC分类号： H01L21/02211 , H01L21/02167 , H01L21/02274 , H01L21/3125 , H01L21/314 , H01L21/76807
摘要： Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.
摘要翻译：提供了用于双镶嵌工艺中的电介质的新型低介电常数材料。通过在等离子体增强化学沉积室中使含氮前体和取代的有机硅烷反应形成低介电常数材料介电层。此外，提供了用于双镶嵌工艺中的钝化或蚀刻停止层的新型低介电常数材料。通过在等离子体增强化学沉积室中使取代的氨前体和取代的有机硅烷反应形成具有低介电约束的碳掺杂的氮化硅钝化或蚀刻停止层。或者，通过在等离子体增强化学沉积室中使取代的有机硅烷反应形成具有低介电常数的碳化硅钝化或蚀刻停止层。此外，描述了形成用于双镶嵌工艺中的钝化，电介质和蚀刻停止层的集成工艺。

47. 发明授权

US06352921B1 Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization 有权
公开(公告)号：US06352921B1
公开(公告)日：2002-03-05
申请号：US09619377
申请日：2000-07-19
申请人： Licheng M. Han , Yi Xu , Joseph Zhifeng Xie , Mei Sheng Zhou , Simon Chooi
发明人： Licheng M. Han , Yi Xu , Joseph Zhifeng Xie , Mei Sheng Zhou , Simon Chooi
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/76807 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.

48. 发明授权

US06331479B1 Method to prevent degradation of low dielectric constant material in copper damascene interconnects 有权
标题翻译：防止铜大马士革互连中低介电常数材料退化的方法
公开(公告)号：US06331479B1
公开(公告)日：2001-12-18
申请号：US09398294
申请日：1999-09-20
申请人： Jianxun Li , Mei Sheng Zhou , Yi Xu , Simon Chooi
发明人： Jianxun Li , Mei Sheng Zhou , Yi Xu , Simon Chooi
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/31144 , H01L21/7681 , H01L21/76811 , H01L21/76835
摘要： A method of fabricating trenches has been achieved. The method may be applied to damascene and dual damascene contacts to prevent damage to organic low dielectric constant materials due to photoresist ashing. A semiconductor substrate is provided. A first dielectric layer is deposited overlying the semiconductor substrate. A first etch stopping layer is deposited overlying the first dielectric layer. A second etch stopping layer is deposited overlying the first etch stopping layer. An optional anti-reflective coating is applied. A photoresist layer is deposited. The photoresist layer is patterned to define openings for planned trenches. The second etch stopping layer is etched through to form a hard mask for the planned trenches. The photoresist layer is stripped away by ashing where the first etch stopping layer protects the first dielectric layer from damage due to the presence of oxygen radicals. The first etch stopping layer is etched through to complete the trenches, and the integrated circuit device is completed.
摘要翻译：已经实现了制造沟槽的方法。该方法可以应用于镶嵌和双镶嵌接触，以防止由于光致抗蚀剂灰化而损坏有机低介电常数材料。提供半导体衬底。沉积在半导体衬底上的第一介电层。第一蚀刻停止层沉积在第一介电层上。第二蚀刻停止层沉积在第一蚀刻停止层上。应用可选的抗反射涂层。沉积光致抗蚀剂层。图案化光致抗蚀剂层以限定计划沟槽的开口。蚀刻第二蚀刻停止层以形成用于所计划的沟槽的硬掩模。光致抗蚀剂层通过灰化被剥离，其中第一蚀刻停止层保护第一介电层免受由于氧自由基的存在的损害。蚀刻第一蚀刻停止层以完成沟槽，并且完成集成电路器件。

49. 发明授权

US06265321B1 Air bridge process for forming air gaps 有权
标题翻译：用于形成气隙的气桥过程
公开(公告)号：US06265321B1
公开(公告)日：2001-07-24
申请号：US09550264
申请日：2000-04-17
申请人： Simon Chooi , Mei-Sheng Zhou , Yi Xu
发明人： Simon Chooi , Mei-Sheng Zhou , Yi Xu
IPC分类号： H01L2100
CPC分类号： H01L21/7682 , H01L21/76807
摘要： A method for reducing RC delay in integrated circuits by lowering the dielectric constant of the intermetal dielectric material between metal interconnects or metal damascene interconnects is described. The dielectric constant of the intermetal dielectric is lowered by introducing air into the intermetal dielectric between metal interconnections. An air bridge comprising a porous material, preferably amorphous silicon, porous silicon oxide, or porous silsesquioxane, is deposited over a layer containing a reactive organic material. An oxygen plasma treatment or an anisotropic etching through the pores in the air bridge layer removes at least a portion of the reactive material, leaving air plugs within the intermetal dielectric.
摘要翻译：描述了通过降低金属互连或金属镶嵌互连之间的金属间电介质材料的介电常数来减小集成电路中的RC延迟的方法。通过在金属互连之间的金属间电介质中引入空气来降低金属间电介质的介电常数。包括多孔材料，优选非晶硅，多孔氧化硅或多孔倍半硅氧烷的空气桥被沉积在含有反应性有机材料的层上。通过空气桥接层中的孔的氧等离子体处理或各向异性蚀刻去除至少一部分反应性材料，从而将空气塞留在金属间电介质内。

50. 发明授权

US06690091B1 Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer 有权
标题翻译：使用氮化硼钝化层，蚀刻停止层和/或盖层的具有降低的电容的镶嵌结构
公开(公告)号：US06690091B1
公开(公告)日：2004-02-10
申请号：US09666316
申请日：2000-09-21
申请人： Simon Chooi , Yi Xu , Mei Sheng Zhou
发明人： Simon Chooi , Yi Xu , Mei Sheng Zhou
IPC分类号： H01L2348
CPC分类号： H01L21/76835 , H01L21/31122 , H01L21/318 , H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A damascene structure with reduced capacitance dielectric stacking comprise a passivation, a first dielectric, an etch stop, a second dielectric and a cap layer over a first conductive layer formed on a semiconductor. The passivation, the etch stop, and the cap layers comprise low dielectric constant materials carbon nitride, boron nitride, or boron carbon nitride. The stack is patterned to form a via opening to the first conductive layer. A trench opening is formed stopping on the etch stop layer. A barrier layer of TaN, WN, TaSiN or Ta and a second conductive material is applied to the openings. Passivation, etch stop, or cap layers can be formed with carbon nitride by magnetron sputtering from a graphite target in a nitrogen atmosphere; boron carbon nitride by magnetron sputtering from a graphite target in a nitrogen and B2H6 atmosphere; or boron nitride by PECVD using B2H6, ammonia, and nitrogen.
摘要翻译：具有减小的电容电介质堆叠的镶嵌结构包括在半导体上形成的第一导电层上的钝化，第一电介质，蚀刻停止层，第二介电层和覆盖层。钝化，蚀刻停止和盖层包括低介电常数材料碳氮化物，氮化硼或氮碳化硼。图案化堆叠以形成到第一导电层的通孔。形成停止在蚀刻停止层上的沟槽开口。将TaN，WN，TaSiN或Ta和第二导电材料的阻挡层施加到开口。钝化，蚀刻停止或盖层可以通过在氮气气氛中的石墨靶磁控溅射由碳氮化物形成; 硼氮化物通过磁控溅射从石墨靶在氮气和B2H6气氛中; 或使用B2H6，氨和氮的PECVD的氮化硼。

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