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41. 发明授权

US5668769A Memory device performance by delayed power-down 失效
标题翻译：内存设备性能延迟掉电
公开(公告)号：US5668769A
公开(公告)日：1997-09-16
申请号：US560229
申请日：1995-11-21
申请人： Tim M. Coffman , Ronald J. Syzdek , Timothy J. Coots , Phat C. Truong , Sung-Wei Lin
发明人： Tim M. Coffman , Ronald J. Syzdek , Timothy J. Coots , Phat C. Truong , Sung-Wei Lin
IPC分类号： G11C11/41 , G11C7/22 , G11C11/409 , G11C7/00
CPC分类号： G11C7/22
摘要： The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.
摘要翻译：本发明的方法防止在高频禁用周期的瞬态电流，并且在最小延迟时间之后禁用直流电流路径，从而降低功耗。本发明包括延迟电路，其功能是防止在低于最小持续时间的间隔下发生芯片禁止时间的DC路径的禁用。结果是由于瞬态电流，内部电力总线上的不期望的电压降的数量减少。该方法检测在最小持续时间之前发生的外部芯片禁止脉冲，然后防止这些脉冲掉电内部直流路径。同时，保持了芯片禁止信号的输出驱动器高阻抗功能。

42. 发明授权

US5636162A Erase procedure 失效
标题翻译：擦除程序
公开(公告)号：US5636162A
公开(公告)日：1997-06-03
申请号：US664013
申请日：1996-06-12
申请人： Tim M. Coffman , Sung-Wei Lin , Phat C. Truong
发明人： Tim M. Coffman , Sung-Wei Lin , Phat C. Truong
IPC分类号： G11C16/02 , G11C16/16 , G11C16/34 , G11C29/12 , G11C16/06
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/3445
摘要： A procedure for erasing a Flash EPROM array (AR) includes applying a series of erase pulses to all of the subarrays (S1, S2, etc.) of a Flash EPROM array (AR) simultaneously. Between each erase pulse, the memory cells (10) of each sub array (S1, S2, etc.) are simultaneously checked one row at a time and one column position at a time, to see whether or not any cell (10) is over-erased. If, at any time during the procedure a cell (10) is found to be over-erased, the over-erased condition is corrected and the erase procedure continues, but with erase pulses applied only to those subarrays (S1, S2, etc.) having non-erased memory cells (10) as in prior-art subarray erase procedures. Under almost all circumstances, the procedure of this invention decreases over-all erase time.
摘要翻译：擦除闪存EPROM阵列（AR）的过程包括同时向闪存EPROM阵列（AR）的所有子阵列（S1，S2等）应用一系列擦除脉冲。在每个擦除脉冲之间，每个子阵列（S1，S2等）的存储单元（10）同时一次检查一行一列，同时检查任何单元（10）是否为过度消失如果在程序过程中发现单元（10）被过度擦除的任何时候，都会修正过擦除状态，擦除过程继续进行，但擦除脉冲仅施加于这些子阵列（S1，S2等））具有如现有技术的子阵列擦除过程中的未擦除的存储器单元（10）。在几乎所有情况下，本发明的程序减少了全部擦除时间。

43. 发明授权

US5422590A High voltage negative charge pump with low voltage CMOS transistors 失效
标题翻译：具有低电压CMOS晶体管的高压负电荷泵
公开(公告)号：US5422590A
公开(公告)日：1995-06-06
申请号：US234433
申请日：1994-04-26
申请人： Tim M. Coffman , Sung-Wei Lin
发明人： Tim M. Coffman , Sung-Wei Lin
IPC分类号： G11C5/14 , G11C16/14 , G11C16/30 , G05F3/16 , G05F1/26
CPC分类号： G11C16/14 , G11C16/30 , G11C5/145
摘要： A system for erasing a memory array in a memory has a supply voltage and a negative charge pump. The negative charge pump system includes (a) circuitry to select a memory array to be erased; (b) for circuitry to switch on the supply voltage Vnn for the charge pump; (c) circuitry to pump the supply voltage Vnn with the charge pump to produce a pumped negative voltage; (d) circuitry to erase the selected array with the pumped negative voltage; (e) circuitry to provide the pumping; and (f) circuitry to provide a discharge path for voltages trapped in the charge pump.
摘要翻译：用于擦除存储器中的存储器阵列的系统具有电源电压和负电荷泵。负电荷泵系统包括（a）选择要擦除的存储器阵列的电路; （b）用于接通电荷泵的电源电压Vnn的电路; （c）用电荷泵泵送电源电压Vnn以产生泵送的负电压的电路; （d）利用泵送负电压擦除所选阵列的电路; （e）提供泵送的电路; 和（f）提供用于电荷泵中捕获的电压的放电路径的电路。

44. 发明授权

US5334550A Method of producing a self-aligned window at recessed intersection of insulating regions 失效
标题翻译：在绝缘区的凹口交叉处制造自对准窗的方法
公开(公告)号：US5334550A
公开(公告)日：1994-08-02
申请号：US4813
申请日：1993-01-15
申请人： David J. McElroy , Sung-Wei Lin , Manzur Gill
发明人： David J. McElroy , Sung-Wei Lin , Manzur Gill
IPC分类号： H01L21/033 , H01L21/266 , H01L21/28 , H01L21/308 , H01L21/74 , H01L21/768 , H01L29/423 , H01L21/76
CPC分类号： H01L21/76802 , H01L21/033 , H01L21/266 , H01L21/28273 , H01L21/3081 , H01L21/743 , H01L29/78
摘要： An integrated circuit structure and process relating to a self-aligned window at the recessed junction of two insulating regions formed on the surface of a semiconductor body. The window may include a trench forming an isolation region between doped semiconductor regions, or may include an electrical conductor connected to a doped semiconductor region, or may include an electrical conductor separated from doped semiconductor regions by an electrical insulator. Embodiments include, but are not limited to, a field-effect transistor, a tunnelling area for a floating gate transistor, and an electrical connection to a doped area of the substrate.
摘要翻译：在半导体本体的表面上形成的两个绝缘区的凹陷结的自对准窗有关的集成电路结构和工艺。窗口可以包括在掺杂半导体区域之间形成隔离区域的沟槽，或者可以包括连接到掺杂半导体区域的电导体，或者可以包括通过电绝缘体与掺杂半导体区域分离的电导体。实施例包括但不限于场效应晶体管，用于浮栅晶体管的隧穿区域以及与衬底的掺杂区域的电连接。

45. 发明授权

US5313432A Segmented, multiple-decoder memory array and method for programming a memory array 失效
标题翻译：分段的多解码器存储器阵列和用于编程存储器阵列的方法
公开(公告)号：US5313432A
公开(公告)日：1994-05-17
申请号：US790122
申请日：1991-11-12
申请人： Sung-Wei Lin , John F. Schreck , Phat C. Truong , David J. McElroy , Harvey J. Stiegler , Benjamin H. Ashmore, Jr. , Manzur Gill
发明人： Sung-Wei Lin , John F. Schreck , Phat C. Truong , David J. McElroy , Harvey J. Stiegler , Benjamin H. Ashmore, Jr. , Manzur Gill
IPC分类号： G11C5/02 , G11C8/12 , G11C16/04 , G11C16/08 , G11C16/12 , G11C16/06
CPC分类号： G11C16/0416 , G11C16/08 , G11C16/12 , G11C5/025 , G11C8/12
摘要： A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.
摘要翻译：非易失性存储器阵列的字线解码系统被分成三个较小的解码子系统（读模式解码子系统，程序/擦除模式解码子系统和段选择解码器子系统）。分段阵列具有小的位线电容，并且需要几个输入连接到每个解码子系统。读模式解码器电路和编程/擦除模式解码器电路分开，允许读模式解码器电路用于高速访问，并允许对高电压操作进行编程/擦除模式解码器电路。掩埋位线段选择晶体管减少了那些晶体管所需的面积。可以在首先检查段的每一行以确定任何过度擦除的单元的存在之后执行擦除。可以通过允许所选段的公共源列线浮动并且将预选的电压放置在适当的字线和漏极 - 列线上来执行编程。

46. 发明授权

US5081055A Method of making electrically-erasable, electrically-programmable read-only memory cell having a tunnel window insulator and forming implanted regions for isolation between wordlines 失效
标题翻译：制造具有隧道窗绝缘体并形成用于字线间隔离的注入区域的电可擦除电可编程只读存储单元的方法
公开(公告)号：US5081055A
公开(公告)日：1992-01-14
申请号：US648248
申请日：1991-01-31
申请人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
发明人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L29/7883
摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ration of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between cells in the wordline direction is by a self-aligned implanted region, in this embodiment.
摘要翻译：使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，以无接触电池布局，增强了易于制造和减小电池尺寸。位线和源极/漏极区域被埋在相对厚的氧化硅之下，这允许控制栅极对浮置栅极电容的有利比例。编程和擦除由位于源的通道侧附近或上方的隧道窗口区域提供。窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。在本实施例中，字线方向上的单元之间的隔离是通过自对准注入区域。

47. 发明授权

US5047981A Bit and block erasing of an electrically erasable and programmable read-only memory array 失效
标题翻译：电可擦除可编程只读存储器阵列的位和块擦除
公开(公告)号：US5047981A
公开(公告)日：1991-09-10
申请号：US374113
申请日：1989-06-30
申请人： Manzur Gill , Sung-Wei Lin , Iano D'Arrigo , David McElroy
发明人： Manzur Gill , Sung-Wei Lin , Iano D'Arrigo , David McElroy
IPC分类号： G11C17/00 , G11C16/02 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , G11C16/16 , H01L27/115 , H01L29/7883
摘要： A method for either block- or bit-erasing is described for an array of EEPROM cells, each having transistor channel regions with subchannels thereof respectively controlled by a floating gate conductor and a control gate. Erasing occurs through a Fowler-Nordheim tunnel window (34) between a source bit line (24) and a floating gate conductor (42) of a selected cell. For one or more selected cells, first and second erasing voltages are selected such that the selected source bit line (24) is more positive than the selected word line (48) by a voltage sufficient to cause excess electrons on the floating gate conductor (42) to be drawn through the tunnel window (34) to the source region (24). The nonselected word lines (48) have a nonerasing voltage impressed thereon that is sufficiently close to that of selected source regions that no erase disturb will occur in nonselected cells.
摘要翻译：描述了用于块单元或位擦除的方法，用于EEPROM单元阵列，每个EEPROM单元具有分别由浮置栅极导体和控制栅极控制的子沟道的晶体管沟道区。通过在所选单元的源极线（24）和浮动栅极导体（42）之间的Fowler-Nordheim隧道窗口（34）进行擦除。对于一个或多个所选择的单元，选择第一和第二擦除电压，使得所选择的源极线（24）比所选择的字线（48）更正，所述电压足以在浮置栅极导体（42）上引起过量的电子）通过隧道窗（34）被拉出到源区（24）。非选择字线（48）具有非常接近于所选择的源极区的非绝缘电压，在非选择的单元中不会发生擦除干扰。

48. 发明授权

US5012307A Electrically-erasable, electrically-programmable read-only memory 失效
标题翻译：电可擦除，电可编程只读存储器
公开(公告)号：US5012307A
公开(公告)日：1991-04-30
申请号：US494060
申请日：1990-03-15
申请人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
发明人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L29/7883
摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between wordlines is also by thick thermal oxide in a preferred embodiment, further improving the coupling ratio. Bitline and wordline spacing may be selected for optimum pitch or aspect ratio. Bitline to substrate capacitance is minimized.
摘要翻译：使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了易于制造和减小电池尺寸。位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。隧道窗口提供的编程和擦除靠近或高于源的通道侧。窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。在优选实施例中，字线之间的隔离也是厚氧化物，进一步提高了耦合比。可以选择位线和字线间距来获得最佳间距或宽高比。位线到基板电容最小化。

49. 发明授权

US4823318A Driving circuitry for EEPROM memory cell 失效
标题翻译： EEPROM存储单元的驱动电路
公开(公告)号：US4823318A
公开(公告)日：1989-04-18
申请号：US239877
申请日：1988-09-02
申请人： Sebastiano D'Arrigo , Giuliano Imondi , Sung-Wei Lin , Manzur Gill
发明人： Sebastiano D'Arrigo , Giuliano Imondi , Sung-Wei Lin , Manzur Gill
IPC分类号： G11C17/00 , G11C16/06 , G11C16/08 , G11C16/12 , G11C16/14 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/08 , G11C16/12 , G11C16/14
摘要： A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising four P-channel transistors and two N-channel transistors as well as four switches. The circuit comprises a two-transistor inverter with a feedback transistor and three isolating transistors that prevent excessive currents and voltages from damaging internal and external circuit components.

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