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1. 发明授权

US5047981A Bit and block erasing of an electrically erasable and programmable read-only memory array 失效
标题翻译：电可擦除可编程只读存储器阵列的位和块擦除
公开(公告)号：US5047981A
公开(公告)日：1991-09-10
申请号：US374113
申请日：1989-06-30
申请人： Manzur Gill , Sung-Wei Lin , Iano D'Arrigo , David McElroy
发明人： Manzur Gill , Sung-Wei Lin , Iano D'Arrigo , David McElroy
IPC分类号： G11C17/00 , G11C16/02 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , G11C16/16 , H01L27/115 , H01L29/7883
摘要： A method for either block- or bit-erasing is described for an array of EEPROM cells, each having transistor channel regions with subchannels thereof respectively controlled by a floating gate conductor and a control gate. Erasing occurs through a Fowler-Nordheim tunnel window (34) between a source bit line (24) and a floating gate conductor (42) of a selected cell. For one or more selected cells, first and second erasing voltages are selected such that the selected source bit line (24) is more positive than the selected word line (48) by a voltage sufficient to cause excess electrons on the floating gate conductor (42) to be drawn through the tunnel window (34) to the source region (24). The nonselected word lines (48) have a nonerasing voltage impressed thereon that is sufficiently close to that of selected source regions that no erase disturb will occur in nonselected cells.
摘要翻译：描述了用于块单元或位擦除的方法，用于EEPROM单元阵列，每个EEPROM单元具有分别由浮置栅极导体和控制栅极控制的子沟道的晶体管沟道区。通过在所选单元的源极线（24）和浮动栅极导体（42）之间的Fowler-Nordheim隧道窗口（34）进行擦除。对于一个或多个所选择的单元，选择第一和第二擦除电压，使得所选择的源极线（24）比所选择的字线（48）更正，所述电压足以在浮置栅极导体（42）上引起过量的电子）通过隧道窗（34）被拉出到源区（24）。非选择字线（48）具有非常接近于所选择的源极区的非绝缘电压，在非选择的单元中不会发生擦除干扰。

2. 发明授权

US5168335A Electrically programmable, electrically erasable memory array cell with field plate 失效
标题翻译：电可编程，电可擦除存储阵列单元与现场板
公开(公告)号：US5168335A
公开(公告)日：1992-12-01
申请号：US741975
申请日：1991-08-06
申请人： Iano D'Arrigo , Manzur Gill , Sung-Wei Lin
发明人： Iano D'Arrigo , Manzur Gill , Sung-Wei Lin
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective source regions (30a, 30b), a shared drain region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) that controls the conductance of a respective subchannel region (74a, 74b) and may be programmed through Fowler-Nordheim electron tunneling through a respective tunnel oxide window (40a, 40b) from a respective source region (30a, 30b). A field plate conductor (40a) controls the conductance of respective subchannel regions (70a, 70b) within each channel region (38a, 38b). A word line or control gate conductor (62) is insulatively disposed adjacent respective third, remaining channel subregions (53a, 53b) and further is disposed insulatively adjacent the floating gates (46a, 46b) to program or erase them.
摘要翻译：在半导体层（10）的表面上形成一对电可擦除的电可编程存储单元，并且包括各自的源极区（30a，30b），共用漏极区（28）和各个沟道区（38a，38b）。每个单元具有控制相应子通道区域（74a，74b）的电导的浮栅导体（46a，46b），并且可以通过Fowler-Nordheim电子隧穿通过相应的隧道氧化物窗（40a，40b）从相应的源区域（30a，30b）。场板导体（40a）控制每个通道区域（38a，38b）内各个子通道区域（70a，70b）的电导。字线或控制栅极导体（62）被绝对地设置在相邻的第三剩余通道子区域（53a，53b）附近，并且还与浮动栅极（46a，46b）绝缘地设置以编程或擦除它们。

3. 发明授权

US5218568A Electrically-erasable, electrically-programmable read-only memory cell, an array of such cells and methods for making and using the same 失效
标题翻译：电可擦除的电可编程只读存储器单元，这样的单元阵列以及制造和使用它们的方法
公开(公告)号：US5218568A
公开(公告)日：1993-06-08
申请号：US809462
申请日：1991-12-17
申请人： Sung-Wei Lin , Manzur Gill , Inn K. Lee
发明人： Sung-Wei Lin , Manzur Gill , Inn K. Lee
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
摘要： An electrically-erasable, electrically-programmable read-only memory cell 10 is formed at a face of a layer of semiconductor 30 of a first conductivity type. A first source/drain region 16 and a second source/drain region 20 are formed in the face of layer of semiconductor 30 of a second conductivity type opposite the first conductivity type and spaced by a first channel area 50. A third source/drain region 18 is formed in the face of semiconductor layer 30 of the second conductivity type spaced from second source/drain region 20 by a second channel area 52. A thick insulator region 44 is formed adjacent at least a portion of second source/drain region 20 and includes a lateral margin of sloped thickness overlying a corresponding lateral margin of second source/drain region 20. The corresponding lateral margin of second source/drain region 20 has a graded dopant concentration directly proportionate with the sloped thickness of the overlying lateral margin of thick insulator region 44. A differentially grown insulator region 54 overlies second source/drain region 20 and includes a lateral margin of sloped thickness. A thin insulator tunneling window 62 overlies an area 60 of second source/drain region 20, tunneling window 62 formed between and spacing the lateral margin of the thick insulator region 44 and the lateral margin of differentially grown insulator region 54. A floating gate conductor 26 is disposed adjacent tunneling window 62 and insulatively adjacent second channel area 52. A control gate conductor 28 is disposed insulatively adjacent floating gate conductor 28. A gate conductor 24 is disposed insulatively adjacent first channel area 50.
摘要翻译：电可擦除的电可编程只读存储单元10形成在第一导电类型的半导体层30的表面。第一源极/漏极区域16和第二源极/漏极区域20形成在与第一导电类型相反并且由第一沟道区域50间隔开的第二导电类型的半导体层30的表面中。第三源极/漏极区域 18形成在第二导电类型的半导体层30的表面上，第二导电类型的第二导电类型与第二源极/漏极区域20间隔开第二沟道区域52.邻近第二源极/漏极区域20的至少一部分形成厚的绝缘体区域44，包括覆盖第二源极/漏极区域20的相应横向边缘的倾斜厚度的横向边缘。第二源极/漏极区域20的对应横向边缘具有与厚度绝缘体的上覆侧边缘的倾斜厚度成正比的渐变掺杂剂浓度差分生长的绝缘体区域54覆盖第二源极/漏极区域20并且包括倾斜厚度的侧向边缘。薄的绝缘体隧道窗口62覆盖在第二源极/漏极区域20的区域60之间，形成在厚绝缘体区域44的侧边缘之间并且间隔着厚的绝缘体区域44的侧边缘和差分生长的绝缘体区域54的横向边缘之间的隧道窗口62.浮动栅极导体26 被布置在相邻的隧道窗口62和绝对相邻的第二通道区域52处。控制栅极导体28被隔离地邻近浮置栅极导体28设置。栅极导体24与第一沟道区域50绝缘地邻近设置。

4. 发明授权

US5155055A Method of making an electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel 失效
标题翻译：制造具有自对准隧道的电可擦除，电可编程只读存储器单元的方法
公开(公告)号：US5155055A
公开(公告)日：1992-10-13
申请号：US685358
申请日：1991-04-15
申请人： Manzur Gill , Sung-Wei Lin , C. Rinn Cleavelin , David J. McElroy
发明人： Manzur Gill , Sung-Wei Lin , C. Rinn Cleavelin , David J. McElroy
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.
摘要翻译：使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

5. 发明授权

US5008721A Electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel 失效
标题翻译：具有自对准隧道的电可擦除电可编程只读存储单元
公开(公告)号：US5008721A
公开(公告)日：1991-04-16
申请号：US494042
申请日：1990-03-15
申请人： Manzur Gill , Sung-Wei Lin , C. Rinn Cleavelin , David J. McElroy
发明人： Manzur Gill , Sung-Wei Lin , C. Rinn Cleavelin , David J. McElroy
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883 , Y10S257/903
摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.
摘要翻译：使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

6. 发明授权

US5187683A Method for programming EEPROM memory arrays 失效
标题翻译： EEPROM存储器阵列编程方法
公开(公告)号：US5187683A
公开(公告)日：1993-02-16
申请号：US576307
申请日：1990-08-31
申请人： Manzur Gill , Sung-Wei Lin , Sebastiano D'Arrigo
发明人： Manzur Gill , Sung-Wei Lin , Sebastiano D'Arrigo
IPC分类号： G11C17/00 , G11C16/02 , G11C16/08 , G11C16/10 , H01L21/8247 , H01L27/115
CPC分类号： G11C16/08 , G11C16/10
摘要： A method is described for programming a semiconductor array of EEPROM cells. A selected cell is connected, by definition, to a selected source-column line, a selected drain-column line and a selected wordline. Each deselected memory cell in the array is connected to a deselected source-column line, a deselected drain-column line and/or a deselected wordline. The method includes preselecting first, second, third, fourth and fifth programming voltages such that the second programming voltage is more positive than the first programming voltage and such that the third, fourth and fifth programming voltages are intermediate between the first and second programming voltages. The first programming voltage is applied at least to a selected column line and to each of the same-type deselected column lines. The third programming voltage is applied to the selected wordline and the fourth programming voltage is applied to each deselected wordline. After a pre-charge time interval, the fifth programming voltage is applied to each same-type deselected column line and, after an optional additional pre-charge time interval, the second programming voltage is applied to the selected wordline. After a program time interval, the third programming voltage is applied to the selected wordline and, after an optional discharge time interval, the first programming voltage is applied to each same-type deselected column line. Each deselected wordline is maintained at the fourth programming voltage for an additional discharge time interval. The third, fourth and fifth programming voltages may have the same value.
摘要翻译：描述了一种用于编程EEPROM单元的半导体阵列的方法。根据定义，所选择的单元格连接到所选择的源列行，所选的排列列线和所选择的字线。阵列中的每个取消选择的存储单元连接到未选择的源 - 列线，取消选择的漏 - 列线和/或未选择的字线。该方法包括预选第一，第二，第三，第四和第五编程电压，使得第二编程电压比第一编程电压更正，并且使得第三，第四和第五编程电压在第一和第二编程电压之间。至少将第一编程电压施加到所选择的列线和每个相同类型的未选择的列线。将第三编程电压施加到所选择的字线，并且将第四编程电压施加到每个取消选择的字线。在预充电时间间隔之后，将第五编程电压施加到每个相同类型的未选择的列线，并且在可选的附加预充电时间间隔之后，将第二编程电压施加到所选择的字线。在编程时间间隔之后，将第三编程电压施加到所选择的字线，并且在可选的放电时间间隔之后，将第一编程电压施加到每个相同类型的未选择的列线。每个取消选择的字线保持在第四个编程电压下一个额外的放电时间间隔。第三，第四和第五编程电压可以具有相同的值。

7. 发明授权

US5156991A Fabricating an electrically-erasable, electrically-programmable read-only memory having a tunnel window insulator and thick oxide isolation between wordlines 失效
标题翻译：制造具有隧道窗绝缘体和字线之间的厚氧化物隔离的电可擦除的电可编程只读存储器
公开(公告)号：US5156991A
公开(公告)日：1992-10-20
申请号：US648087
申请日：1991-01-31
申请人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
发明人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L29/7883 , Y10S438/981
摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between wordlines is also by thick thermal oxide in a preferred embodiment, further improving the coupling ratio. Bitline and wordline spacing may be selected for optimum pitch or aspect ratio. Bitline to substrate capacitance is minimized.
摘要翻译：使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了易于制造和减小电池尺寸。位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。隧道窗口提供的编程和擦除靠近或高于源的通道侧。窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。在优选实施例中，字线之间的隔离也是厚氧化物，进一步提高了耦合比。可以选择位线和字线间距来获得最佳间距或宽高比。位线到基板电容最小化。

8. 发明授权

US5334550A Method of producing a self-aligned window at recessed intersection of insulating regions 失效
标题翻译：在绝缘区的凹口交叉处制造自对准窗的方法
公开(公告)号：US5334550A
公开(公告)日：1994-08-02
申请号：US4813
申请日：1993-01-15
申请人： David J. McElroy , Sung-Wei Lin , Manzur Gill
发明人： David J. McElroy , Sung-Wei Lin , Manzur Gill
IPC分类号： H01L21/033 , H01L21/266 , H01L21/28 , H01L21/308 , H01L21/74 , H01L21/768 , H01L29/423 , H01L21/76
CPC分类号： H01L21/76802 , H01L21/033 , H01L21/266 , H01L21/28273 , H01L21/3081 , H01L21/743 , H01L29/78
摘要： An integrated circuit structure and process relating to a self-aligned window at the recessed junction of two insulating regions formed on the surface of a semiconductor body. The window may include a trench forming an isolation region between doped semiconductor regions, or may include an electrical conductor connected to a doped semiconductor region, or may include an electrical conductor separated from doped semiconductor regions by an electrical insulator. Embodiments include, but are not limited to, a field-effect transistor, a tunnelling area for a floating gate transistor, and an electrical connection to a doped area of the substrate.
摘要翻译：在半导体本体的表面上形成的两个绝缘区的凹陷结的自对准窗有关的集成电路结构和工艺。窗口可以包括在掺杂半导体区域之间形成隔离区域的沟槽，或者可以包括连接到掺杂半导体区域的电导体，或者可以包括通过电绝缘体与掺杂半导体区域分离的电导体。实施例包括但不限于场效应晶体管，用于浮栅晶体管的隧穿区域以及与衬底的掺杂区域的电连接。

9. 发明授权

US5313432A Segmented, multiple-decoder memory array and method for programming a memory array 失效
标题翻译：分段的多解码器存储器阵列和用于编程存储器阵列的方法
公开(公告)号：US5313432A
公开(公告)日：1994-05-17
申请号：US790122
申请日：1991-11-12
申请人： Sung-Wei Lin , John F. Schreck , Phat C. Truong , David J. McElroy , Harvey J. Stiegler , Benjamin H. Ashmore, Jr. , Manzur Gill
发明人： Sung-Wei Lin , John F. Schreck , Phat C. Truong , David J. McElroy , Harvey J. Stiegler , Benjamin H. Ashmore, Jr. , Manzur Gill
IPC分类号： G11C5/02 , G11C8/12 , G11C16/04 , G11C16/08 , G11C16/12 , G11C16/06
CPC分类号： G11C16/0416 , G11C16/08 , G11C16/12 , G11C5/025 , G11C8/12
摘要： A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.
摘要翻译：非易失性存储器阵列的字线解码系统被分成三个较小的解码子系统（读模式解码子系统，程序/擦除模式解码子系统和段选择解码器子系统）。分段阵列具有小的位线电容，并且需要几个输入连接到每个解码子系统。读模式解码器电路和编程/擦除模式解码器电路分开，允许读模式解码器电路用于高速访问，并允许对高电压操作进行编程/擦除模式解码器电路。掩埋位线段选择晶体管减少了那些晶体管所需的面积。可以在首先检查段的每一行以确定任何过度擦除的单元的存在之后执行擦除。可以通过允许所选段的公共源列线浮动并且将预选的电压放置在适当的字线和漏极 - 列线上来执行编程。

10. 发明授权

US5081055A Method of making electrically-erasable, electrically-programmable read-only memory cell having a tunnel window insulator and forming implanted regions for isolation between wordlines 失效
标题翻译：制造具有隧道窗绝缘体并形成用于字线间隔离的注入区域的电可擦除电可编程只读存储单元的方法
公开(公告)号：US5081055A
公开(公告)日：1992-01-14
申请号：US648248
申请日：1991-01-31
申请人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
发明人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L29/7883
摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ration of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between cells in the wordline direction is by a self-aligned implanted region, in this embodiment.
摘要翻译：使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，以无接触电池布局，增强了易于制造和减小电池尺寸。位线和源极/漏极区域被埋在相对厚的氧化硅之下，这允许控制栅极对浮置栅极电容的有利比例。编程和擦除由位于源的通道侧附近或上方的隧道窗口区域提供。窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。在本实施例中，字线方向上的单元之间的隔离是通过自对准注入区域。

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