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1. 发明申请

US20070022332A1 Background block erase check for flash memories 失效
标题翻译：背景块擦除检查闪存
公开(公告)号：US20070022332A1
公开(公告)日：2007-01-25
申请号：US11519415
申请日：2006-09-12
申请人： Giuliano Imondi , Giovanni Naso
发明人： Giuliano Imondi , Giovanni Naso
IPC分类号： G01R31/28
CPC分类号： G11C16/3445 , G11C16/344
摘要： Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check operations. Such apparatus and methods facilitate subsequent checks for data gain of erased memory cells using abbreviated procedures compared to normal erase operations.
摘要翻译：操作存储器件的存储器件和方法在擦除验证操作期间提供使用不同的电位，便于正常擦除操作和随后的擦除检查操作。与普通擦除操作相比，这种装置和方法便于使用缩写的过程随后检查擦除的存储器单元的数据增益。

2. 发明授权

US5299286A Data processing system for implementing architecture of neural network subject to learning process 失效
标题翻译：用于实现学习过程中神经网络架构的数据处理系统
公开(公告)号：US5299286A
公开(公告)日：1994-03-29
申请号：US828077
申请日：1992-01-30
申请人： Giuliano Imondi , Giulio Marotta , Giulio Porrovecchio , Giuseppe Savarese , Luciano Talamonti
发明人： Giuliano Imondi , Giulio Marotta , Giulio Porrovecchio , Giuseppe Savarese , Luciano Talamonti
IPC分类号： G06N3/063 , G06F15/40
CPC分类号： G06N3/063
摘要： Data processing system implementing architecture of a neural network which is subject to a learning process, wherein the data processing system includes n.times.n synapses arranged in an array of j rows and i columns. A plurality of operational amplifiers respectively corresponding to the rows of the array are provided, with each operational amplifier defining a neuron. The input terminals of all of the synapses arranged in a respective column of the array are connected together and define n inputs of the neural network. The output terminals of the synapses arranged in a respective row of the array are connected together and serve as the inputs to a corresponding one of the plurality of operational amplifiers. Each synapse includes a capacitor connected between ground potential and the input terminal for weighting the synapse by storing a weighting voltage applied thereto. A random access memory has digitally stored voltage values for weighting all of the synapses. A plurality of digital-analog converters, one for each column of the array of synapses, are connected to the random access memory for converting the digital voltage values for weighting the synapses into analog voltage values. The digital-analog converters provide respective outputs to the weighting terminals of the synapses of a column via respective electronic switches for each synapse. Each row of the array includes a bistable circuit for driving the respective electronic switches under the control of a control section which also provides function commands and data to the random access memory.
摘要翻译：实施受学习过程的神经网络的架构的数据处理系统，其中所述数据处理系统包括以j行和i列的阵列排列的n * n个突触。分别对应于阵列行的多个运算放大器，每个运算放大器定义一个神经元。布置在阵列的相应列中的所有突触的输入端子连接在一起并定义神经网络的n个输入。布置在阵列的相应行中的突触的输出端子连接在一起，并用作对多个运算放大器中的相应一个的输入。每个突触包括连接在地电位和输入端之间的电容器，用于通过存储施加于其上的加权电压来加权突触。随机存取存储器具有用于加权所有突触的数字存储的电压值。多个数字 - 模拟转换器（每个突触阵列中的一列）连接到随机存取存储器，用于将用于加权突触的数字电压值转换为模拟电压值。数字 - 模拟转换器通过用于每个突触的各个电子开关向列的突触的加权终端提供相应的输出。该阵列的每行包括用于在控制部分的控制下驱动各个电子开关的双稳态电路，控制部分还向随机存取存储器提供功能命令和数据。

3. 发明申请

US20050270879A1 No-precharge FAMOS cell and latch circuit in a memory device 有权
公开(公告)号：US20050270879A1
公开(公告)日：2005-12-08
申请号：US11196913
申请日：2005-08-04
申请人： Giuliano Imondi
发明人： Giuliano Imondi
IPC分类号： G11C16/26 , G11C17/16 , G11C5/00
CPC分类号： G11C16/26 , G11C29/789
摘要： The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit. The transmission gate isolates the fuse from the latch. When a reset condition occurs, the data that was in latch circuit remains after the reset condition is complete.

4. 发明授权

US4823320A Electrically programmable fuse circuit for an integrated-circuit chip 失效
标题翻译：用于集成电路芯片的电可编程熔丝电路
公开(公告)号：US4823320A
公开(公告)日：1989-04-18
申请号：US860940
申请日：1986-05-08
申请人： Michael C. Smayling , Sebastiano D'Arrigo , Giuliano Imondi , Sossio Vergara
发明人： Michael C. Smayling , Sebastiano D'Arrigo , Giuliano Imondi , Sossio Vergara
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26 , G11C7/00
CPC分类号： G11C16/26 , G11C16/0441 , G11C16/10
摘要： A fuse circuit for an integrated circuit chip which includes a non-volatile memory element, a circuit programmer for the memory element, and a read circuit for detecting the programmed states of the memory element and providing output signal levels corresponding to the programmed states. A switch is coupled to the read circuit output and switches from an open to a closed position in response to a selected output signal level.
摘要翻译：一种用于集成电路芯片的熔丝电路，其包括非易失性存储器元件，用于存储元件的电路编程器，以及用于检测存储器元件的编程状态并提供与编程状态相对应的输出信号电平的读取电路。开关耦合到读取电路输出，并响应于所选择的输出信号电平从开路切换到闭合位置。

5. 发明授权

US4760555A Memory array with an array reorganizer 失效
标题翻译：具有阵列重组器的内存阵列
公开(公告)号：US4760555A
公开(公告)日：1988-07-26
申请号：US854229
申请日：1986-04-21
申请人： Tito Gelsomini , Giuliano Imondi
发明人： Tito Gelsomini , Giuliano Imondi
IPC分类号： G11C16/10 , G11C16/26 , G11C11/40
CPC分类号： G11C16/26 , G11C16/10
摘要： A non-volatile memory device formed on a face of a semiconductor substrate which includes an array of electrically programmable read only memory cells, a Y address decoder coupled to said array and first and second sets of input/output lines coupled to said Y address decoder. Switch means isolates either the first or second set of input/output lines from the Y decoder. A programmable non-volatile memory element is coupled to programming ones of the input lines and is programmable into a programmed state from an unprogrammed state in response to a programming voltage applied to programming ones of the first set of input lines. A control circuit is coupled to the switch means and to the memory element for isolating the first or second set in response to an external signal applied to a selecting one of the first set of input/output lines and in response to the state of the non-volatile memory element.
摘要翻译：一种形成在半导体衬底的表面上的非易失性存储器件，其包括电可编程只读存储器单元阵列，耦合到所述阵列的Y地址解码器以及耦合到所述Y地址解码器的第一组和第二组输入/输出线。开关装置将第一组或第二组输入/输出线与Y解码器隔离开。可编程非易失性存储器元件耦合到编程输入线路，并且响应于施加到编程第一组输入线路的编程电压而从未编程状态将其编程为编程状态。控制电路耦合到开关装置和存储器元件，用于响应于施加到第一组输入/输出线路中的选择一个的外部信号并且响应于非 - 非易失存储元件。

6. 发明授权

US4706011A High voltage pulse detector with controllable current consumption 失效
标题翻译：高电压脉冲检测器，可控电流消耗
公开(公告)号：US4706011A
公开(公告)日：1987-11-10
申请号：US882557
申请日：1986-07-07
申请人： Sossio Vergara , Sebastiano D'Arrigo , Giuliano Imondi
发明人： Sossio Vergara , Sebastiano D'Arrigo , Giuliano Imondi
IPC分类号： H03K5/05 , G05F1/565 , H03K5/08
CPC分类号： G05F1/565
摘要： A circuit for sensing a voltage present on an input line higher than a supply voltage V.sub.DD which includes an isolation switch coupled between the input line and an output line, a threshold adjustment diode coupled in series with the isolation switch also between the input and output lines for establishing a voltage above V.sub.DD at which the isolation switch turns on and a constant current source coupled from an output of the sensing circuit and ground.
摘要翻译：用于感测存在于高于电源电压VDD的输入线路上的电压的电路，其包括耦合在输入线路和输出线路之间的隔离开关，阈值调节二极管也与输入和输出线路之间的隔离开关串联耦合用于建立高于VDD的电压，隔离开关导通，以及从感测电路的输出和接地耦合的恒定电流源。

7. 发明授权

US4736342A Method of forming a field plate in a high voltage array 失效
标题翻译：在高压阵列中形成场板的方法
公开(公告)号：US4736342A
公开(公告)日：1988-04-05
申请号：US798269
申请日：1985-11-15
申请人： Giuliano Imondi , Michael C. Smayling , Sossio Vergara , Sebastiano D'Arrigo
发明人： Giuliano Imondi , Michael C. Smayling , Sossio Vergara , Sebastiano D'Arrigo
IPC分类号： H01L21/8247 , G11C16/04 , G11C17/00 , H01L21/8246 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34 , G11C8/00
CPC分类号： H01L27/115 , G11C16/0441
摘要： An array of electrically programmable semiconductor memory cells of a type having electrically conducting odd and even row lines, left and right column and ground lines and field oxide regions separating adjacent left and right cells. The array has a field plate over the field oxide region which extends underneath both odd and even row lines. A driver is coupled to the odd and even row lines in order to drive one of them to substantially ground potential while the other is driven high to a cell selection voltage.
摘要翻译：一种具有导电奇数和偶数行线，左右列和接地线的电可编程半导体存储器单元的阵列和分隔相邻的左右单元的场氧化物区域。该阵列在场氧化物区域上具有场板，其延伸在奇数行和偶数行之下。驱动器耦合到奇数行和偶数行，以便驱动它们中的一个基本上接地电位，而另一个被驱动到高电平单元选择电压。

8. 发明授权

US4652837A Integrated circuit oscillator 失效
标题翻译：集成电路振荡器
公开(公告)号：US4652837A
公开(公告)日：1987-03-24
申请号：US798268
申请日：1985-11-15
申请人： Sebastiano D'Arrigo , Giuliano Imondi , Sossio Vergara
发明人： Sebastiano D'Arrigo , Giuliano Imondi , Sossio Vergara
IPC分类号： H03K3/0231 , H03K5/15 , H03K3/02
CPC分类号： H03K3/0231 , H03K5/1506
摘要： An oscillator for an integrated circuit which includes a Schmitt trigger having an upper threshold voltage V.sub.H and a lower threshold voltage V.sub.L, a capacitor coupled between an input to the trigger and ground, a current generator coupled to the trigger input for charging the capacitor at a constant rate and a current generator coupled to the trigger input for discharging the capacitor at a constant rate. A charge switch in series with the charging current generator reversibly couples the charging current generator between a source of high voltage and the trigger input in response to a change in state of the trigger from a first state to a second state. A discharge switch in series with the discharging current generator reversibly couples the latter across the capacitor in response to a change in state of the trigger from the second state to the first state.
摘要翻译：一种用于集成电路的振荡器，其包括具有上阈值电压VH和较低阈值电压VL的施密特触发器，耦合到触发器和地之间的电容器，耦合到触发输入端的电流发生器，用于在电容器恒定速率和耦合到触发输入的电流发生器，以恒定速率放电电容器。与充电电流发生器串联的充电开关响应于触发器的状态从第一状态到第二状态而将充电电流发生器可逆地耦合在高电压源和触发输入之间。与放电电流发生器串联的放电开关响应于触发器的状态从第二状态到第一状态而将电容器可逆地耦合到电容器两端。

9. 发明申请

US20050207233A1 Dual bus memory burst architecture 有权
标题翻译：双总线内存突发架构
公开(公告)号：US20050207233A1
公开(公告)日：2005-09-22
申请号：US11142114
申请日：2005-06-01
申请人： Girolamo Gallo , Giuliano Imondi , Giovanni Naso , Tommaso Vali
发明人： Girolamo Gallo , Giuliano Imondi , Giovanni Naso , Tommaso Vali
IPC分类号： G11C7/10 , G11C5/00
CPC分类号： G11C7/106 , G11C7/1021 , G11C7/103 , G11C7/1051 , G11C7/1066
摘要： Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.
摘要翻译：包括突发体系结构的存储器件的方法和装置采用复用到输出总线上的双总线架构。所产生的架构有效地增加了吞吐量，而不会增加内存设备的延迟。

10. 发明授权

US5457771A Integrated circuit with non-volatile, variable resistor, for use in neuronic network 失效
标题翻译：具有非易失性，可变电阻的集成电路，用于神经网络
公开(公告)号：US5457771A
公开(公告)日：1995-10-10
申请号：US762817
申请日：1991-09-18
申请人： Giuliano Imondi , Giulio Marotta , Eros Pasero , Giulio Porrovecchio , Giuseppe Savarese
发明人： Giuliano Imondi , Giulio Marotta , Eros Pasero , Giulio Porrovecchio , Giuseppe Savarese
IPC分类号： G11C11/54 , G06N3/063 , G11C16/04 , G11C17/00 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/86
CPC分类号： G06N3/0635 , H01L27/105 , H01L27/115
摘要： Integrated circuit with a non-volatile variable resistor which is particularly adapted for use in a neuronic network. The integrated circuit comprises a symmetrically replicated structure including a floating gate MOS transistor (TRP; TRN) and an EEPROM memory cell based upon N-channel MOS transistors and including a read-out MOS transistor (TSP; TSN) and a tunnel-effect charge injection MOS element (TUNP; TUNN), with floating gates. The floating gates of all transistors and of the tunnel-effect element are connected together, with the ends of the resistor (R1P, R2P; R1N, R2N) being taken out from the source and drain regions of the floating gate MOS transistor.
摘要翻译：具有非易失性可变电阻器的集成电路，其特别适用于神经网络。集成电路包括对称复制结构，包括浮置栅极MOS晶体管（TRP; TRN）和基于N沟道MOS晶体管的EEPROM存储单元，并且包括读出的MOS晶体管（TSP; TSN）和隧道效应电荷注入MOS元件（TUNP; TUNN），带浮动栅极。所有晶体管和隧道效应元件的浮置栅极连接在一起，电阻（R1P，R2P; R1N，R2N）的端部从浮置栅极MOS晶体管的源极和漏极区域中取出。

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