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1. 发明授权

US5047981A Bit and block erasing of an electrically erasable and programmable read-only memory array 失效
标题翻译：电可擦除可编程只读存储器阵列的位和块擦除
公开(公告)号：US5047981A
公开(公告)日：1991-09-10
申请号：US374113
申请日：1989-06-30
申请人： Manzur Gill , Sung-Wei Lin , Iano D'Arrigo , David McElroy
发明人： Manzur Gill , Sung-Wei Lin , Iano D'Arrigo , David McElroy
IPC分类号： G11C17/00 , G11C16/02 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , G11C16/16 , H01L27/115 , H01L29/7883
摘要： A method for either block- or bit-erasing is described for an array of EEPROM cells, each having transistor channel regions with subchannels thereof respectively controlled by a floating gate conductor and a control gate. Erasing occurs through a Fowler-Nordheim tunnel window (34) between a source bit line (24) and a floating gate conductor (42) of a selected cell. For one or more selected cells, first and second erasing voltages are selected such that the selected source bit line (24) is more positive than the selected word line (48) by a voltage sufficient to cause excess electrons on the floating gate conductor (42) to be drawn through the tunnel window (34) to the source region (24). The nonselected word lines (48) have a nonerasing voltage impressed thereon that is sufficiently close to that of selected source regions that no erase disturb will occur in nonselected cells.
摘要翻译：描述了用于块单元或位擦除的方法，用于EEPROM单元阵列，每个EEPROM单元具有分别由浮置栅极导体和控制栅极控制的子沟道的晶体管沟道区。通过在所选单元的源极线（24）和浮动栅极导体（42）之间的Fowler-Nordheim隧道窗口（34）进行擦除。对于一个或多个所选择的单元，选择第一和第二擦除电压，使得所选择的源极线（24）比所选择的字线（48）更正，所述电压足以在浮置栅极导体（42）上引起过量的电子）通过隧道窗（34）被拉出到源区（24）。非选择字线（48）具有非常接近于所选择的源极区的非绝缘电压，在非选择的单元中不会发生擦除干扰。

2. 发明授权

US5557569A Low voltage flash EEPROM C-cell using fowler-nordheim tunneling 失效
标题翻译：低压闪存EEPROM C-cell使用fowler-nordheim隧道
公开(公告)号：US5557569A
公开(公告)日：1996-09-17
申请号：US453474
申请日：1995-05-25
申请人： Michael C. Smayling , Giulio G. Marotta , Iano D'Arrigo , Giovanni Santin , Georges Falessi , Mousumi Bhat
发明人： Michael C. Smayling , Giulio G. Marotta , Iano D'Arrigo , Giovanni Santin , Georges Falessi , Mousumi Bhat
IPC分类号： G11C16/04 , G11C16/08 , H01L27/115
CPC分类号： G11C16/0416 , G11C16/0433 , G11C16/08 , H01L27/115
摘要： A low voltage flash EEPROM X-Cell includes an array of memory cell transistors (24) that constitute asymmetric floating gate memory cells wherein programming is achieved on only one side of the memory cells (24). The programming side of each of the memory cells (24) is connected to one of a plurality of Column Lines (28) at nodes (30). Each node (30) shares the programming side of two of the memory cells (24) and the non-programming side of two of the memory cells (24). The control gates of each of the memory cells (24) are connected to Word Lines (26) associated with rows of the array. To Flash Write all of the memory cells (24), the Column Lines (38) are connected to a negative medium voltage and the row lines (26) are connected to a positive medium voltage. To selectively erase one of the memory cells (24), the Column Line (28) associated with the programming side of the select memory cell transistor is connected to a positive medium voltage and the associated line (26) is connected to a positive Read voltage. The remaining Word Lines are connected to a negative Read voltage and the remaining Column Lines (28) are connected to a zero volt level.
摘要翻译：低电压快闪EEPROM X-Cell包括构成非对称浮动栅极存储单元的存储单元晶体管阵列（24），其中仅在存储单元（24）的一侧实现编程。每个存储器单元（24）的编程侧在节点（30）处连接到多个列线（28）中的一个。每个节点（30）共享两个存储器单元（24）的两个存储器单元（24）的非编程侧的编程侧。每个存储器单元（24）的控制栅极连接到与阵列的行相关联的字线（26）。闪存写入所有存储单元（24），列线（38）连接到负中等电压，行线（26）连接到正中压。为了选择性地擦除存储器单元（24）中的一个，与选择存储单元晶体管的编程侧相关联的列线（28）连接到正的中间电压，并且相关的线路（26）连接到正的读取电压。剩下的字线连接到负的读取电压，剩余的列线（28）连接到零伏电平。

3. 发明授权

US5504706A Low voltage Fowler-Nordheim flash EEPROM memory array utilizing single level poly cells 失效
标题翻译：低电压Fowler-Nordheim闪存EEPROM存储阵列，采用单层聚合电池
公开(公告)号：US5504706A
公开(公告)日：1996-04-02
申请号：US135696
申请日：1993-10-12
申请人： Iano D'Arrigo , Georges Falessi , Michael C. Smayling
发明人： Iano D'Arrigo , Georges Falessi , Michael C. Smayling
IPC分类号： G11C16/04 , H01L27/115 , H01L29/788 , G11C11/34 , H01L29/68
CPC分类号： H01L27/115 , G11C16/0416 , H01L29/7883 , G11C2216/10 , G11C2216/16 , G11C2216/18
摘要： A memory array (10) is provided with a plurality of Flash EEPROM memory cells (24) that are fabricated with a single level poly process. Each of the transistor cells (24) is fabricated from a single poly layer floating gate (40) that extends between a moat region (30) and an implanted region (80), comprising the control gate of the cell (24). The portion of the floating gate (40) overlying the moat forms a channel region and is separated therefrom by a thin tunnel oxide layer (82) to allow the cell to operate in accordance with Fowler-Nordheim tunneling. The portion of the floating gate (40) disposed over the implanted control gate (80) is separated therefrom by a layer of oxide (84). The implant region (80) is contacted by a contact layer (86) to allow voltage to be applied thereto. The transistor is contained within a P-tank (78) which is disposed at a negative voltage, this tank (78) contained within an N-tank (76), which tank ( 76) is disposed at a higher voltage. This assures that no conduction occurs from the region (80) to the tank (78) when negative voltages are applied to the control gate. Negative medium voltages and positive medium voltages are utilized to allow the array to be bit programmed without using separate row select transistors.
摘要翻译：存储器阵列（10）设置有多个闪存EEPROM存储器单元（24），其被制造为单级多工艺。每个晶体管单元（24）由包括电池（24）的控制栅极的沟槽区域（30）和注入区域（80）之间延伸的单个多晶硅浮动栅极（40）制成。覆盖在护城河上的浮动栅极（40）的部分形成沟道区域，并且通过薄的隧道氧化物层（82）与其隔开，以允许电池根据福勒 - 诺德海姆隧道进行操作。设置在植入的控制栅极（80）上方的浮置栅极（40）的部分与氧化层（84）分离。植入区域（80）由接触层（86）接触以允许施加电压。晶体管被包含在设置在负电压的P型罐（78）内，该罐（78）包含在N-罐（76）内，该罐（76）被设置在较高的电压。这确保当负电压施加到控制栅极时，从区域（80）到罐（78）不会发生导通。利用负的中等电压和正的中等电压来使阵列被编程，而不使用单独的行选择晶体管。

4. 发明授权

US5467307A Memory array utilizing low voltage Fowler-Nordheim Flash EEPROM cell 失效
标题翻译：采用低电压Fowler-Nordheim闪存EEPROM单元的存储阵列
公开(公告)号：US5467307A
公开(公告)日：1995-11-14
申请号：US135694
申请日：1993-10-12
申请人： Iano D'Arrigo , Georges Falessi , Michael C. Smayling
发明人： Iano D'Arrigo , Georges Falessi , Michael C. Smayling
IPC分类号： G11C8/08 , G11C16/04 , H01L27/115 , G11C11/34
CPC分类号： G11C16/0416 , G11C8/08 , H01L27/115
摘要： A Flash EEPROM memory array includes a plurality of transistor memory cells (24) arranged in rows and columns. The sources of the transistors (24) are connected to Virtual Ground Lines (29) and the drains thereof are connected to Column Lines (28). The memory cells (24) are programmable by Fowler-Nordheim tunneling. Each cell also includes an isolation structure having a first isolation tank of the first conductivity type material for surrounding each of the floating gate transistor memory devices and a second isolation tank of a second conductivity type material opposite to the first conductivity type surrounding the first isolation tank, allowing application of a negative voltage to the source or drain of the cell. Initially, all of the transistors are erased in the FLASH ERASE operation by disposing the Word Lines at a negative medium voltage and the Bit Lines at a positive medium voltage. Thereafter, selected transistors can be written to by selectively charging the floating gates in the transistors. This is achieved by disposing the Column Lines (28) of a select transistor at a negative voltage of a magnitude less than the programming voltage V.sub. PP and disposing the row line (26) of the select transistor at a positive voltage of a magnitude less than V.sub.PP.
摘要翻译：闪存EEPROM存储器阵列包括以行和列布置的多个晶体管存储单元（24）。晶体管（24）的源极连接到虚拟接地线（29），其漏极连接到列线（28）。存储器单元（24）可由Fowler-Nordheim隧道编程。每个单元还包括隔离结构，该隔离结构具有第一导电类型材料的第一隔离槽，用于围绕每个浮栅晶体管存储器件;以及第二隔离槽，其与围绕第一隔离槽的第一导电类型相反的第二导电类型材料允许向电池的源极或漏极施加负电压。最初，在闪存擦除操作中，所有晶体管都通过将字线置于负中压而位线位于正中压。此后，可以通过选择性地对晶体管中的浮置栅极充电来写入所选择的晶体管。这通过将选择晶体管的列线（28）设置在小于编程电压V PP的量级的负电压并将选择晶体管的行线（26）设置在小于 VPP。

5. 发明授权

US5515319A Non-volatile memory cell and level shifter 失效
标题翻译：非易失性存储单元和电平转换器
公开(公告)号：US5515319A
公开(公告)日：1996-05-07
申请号：US135935
申请日：1993-10-12
申请人： Michael C. Smayling , Iano D'Arrigo , Giovanni Santin , Georges Falessi , Mousumi Bhat
发明人： Michael C. Smayling , Iano D'Arrigo , Giovanni Santin , Georges Falessi , Mousumi Bhat
IPC分类号： G11C16/10 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , G11C7/00
CPC分类号： H01L27/11526 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7885
摘要： A non-volatile memory cell 10 is disclosed herein. The cell is formed in a first semiconductor region 12 of a first conductivity type. A second semiconductor region 14 of a second conductivity type formed over the first semiconductor region 12. A third semiconductor region 16 of the first conductivity type formed over the second semiconductor region 14. In the preferred embodiment, the second and third regions 14 and 16 are well regions formed within the first region 12. Other regions such as epitaxially grown layers can also be used. First and second source/drain regions 18 and 20 are formed within the third semiconductor region 16. These second source/drain regions 18 and 20 are separated by a channel region 22. A floating gate 26 overlies at least a portion of the channel region 22 while a control gate 30 overlies the floating gate 26.
摘要翻译：本文公开了非易失性存储单元10。电池形成在第一导电类型的第一半导体区域12中。形成在第一半导体区域12上的第二导电类型的第二半导体区域14.在第二半导体区域14上形成的第一导电类型的第三半导体区域16.在优选实施例中，第二和第三区域14和16是形成在第一区域12内的阱区。也可以使用其它区域，例如外延生长层。第一和第二源极/漏极区域18和20形成在第三半导体区域16内。这些第二源极/漏极区域18和20被沟道区域22分开。浮置栅极26覆盖沟道区域22的至少一部分而控制门30覆盖浮动门26。

6. 发明授权

US5432740A Low voltage flash EEPROM memory cell with merge select transistor and non-stacked gate structure 失效
标题翻译：具有合并选择晶体管和非堆叠栅极结构的低电压快闪EEPROM存储单元
公开(公告)号：US5432740A
公开(公告)日：1995-07-11
申请号：US135813
申请日：1993-10-12
申请人： Iano D'Arrigo , Georges Falessi , Michael C. Smayling
发明人： Iano D'Arrigo , Georges Falessi , Michael C. Smayling
IPC分类号： G11C16/04 , H01L27/115 , G11C7/00
CPC分类号： G11C16/0433 , H01L27/115
摘要： A EEPROM memory array (10) includes a plurality of memory cells (24) which are connected in a symmetric array between row lines (26) and Column Lines (28) and Virtual Ground Lines (29). Each of the memory cells includes a merged pass gate which is connected to a control gate. A non-stacked structure is utilized wherein a floating gate (42) is formed, having two portions that extend over an active region, a tunnel diode portion (44) and a control gate portion (46). The floating gate portion (44) is disposed over a thin tunnel oxide layer (47) to form a tunnel diode which allows Fowler-Nordheim tunneling to occur. The control gate portion (46) is disposed over a much thicker oxide layer such that tunneling does not occur. A control gate layer (50) is disposed over the floating gate (42) such that it overlaps the edges thereof and encloses the floating gate (42). On the one side of the floating gate (42), the control gate extends over the gate oxide layer in an extended portion (52) to form a pass gate structure. The pass gate structure is a merged structure formed in series with the floating gate cell. The merged pass gate has a controllable threshold that allows the floating gate cell to be overerased without causing unwanted conduction when the cell is unselected.
摘要翻译： EEPROM存储器阵列（10）包括在行线（26）和列线（28）和虚拟接地线（29）之间以对称阵列连接的多个存储器单元（24）。每个存储单元包括连接到控制门的合并通道。使用非堆叠结构，其中形成浮动栅极（42），其具有在有源区域上延伸的两个部分，隧道二极管部分（44）和控制栅极部分（46）。浮动栅极部分（44）设置在薄的隧道氧化物层（47）上，以形成允许发生Fowler-Nordheim隧道的隧道二极管。控制栅极部分（46）设置在更厚的氧化物层上，使得隧道不发生。控制栅极层（50）设置在浮动栅极（42）上，使得它与其边缘重叠并且包围浮动栅极（42）。在浮动栅极（42）的一侧上，控制栅极延伸在延伸部分（52）上的栅极氧化物层上，以形成栅极结构。通栅结构是与浮栅单元串联形成的合并结构。合并的通过门具有可控的阈值，允许浮动单元在未选择单元时不会导致不必要的导通而过渡。

7. 发明授权

US5168335A Electrically programmable, electrically erasable memory array cell with field plate 失效
标题翻译：电可编程，电可擦除存储阵列单元与现场板
公开(公告)号：US5168335A
公开(公告)日：1992-12-01
申请号：US741975
申请日：1991-08-06
申请人： Iano D'Arrigo , Manzur Gill , Sung-Wei Lin
发明人： Iano D'Arrigo , Manzur Gill , Sung-Wei Lin
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective source regions (30a, 30b), a shared drain region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) that controls the conductance of a respective subchannel region (74a, 74b) and may be programmed through Fowler-Nordheim electron tunneling through a respective tunnel oxide window (40a, 40b) from a respective source region (30a, 30b). A field plate conductor (40a) controls the conductance of respective subchannel regions (70a, 70b) within each channel region (38a, 38b). A word line or control gate conductor (62) is insulatively disposed adjacent respective third, remaining channel subregions (53a, 53b) and further is disposed insulatively adjacent the floating gates (46a, 46b) to program or erase them.
摘要翻译：在半导体层（10）的表面上形成一对电可擦除的电可编程存储单元，并且包括各自的源极区（30a，30b），共用漏极区（28）和各个沟道区（38a，38b）。每个单元具有控制相应子通道区域（74a，74b）的电导的浮栅导体（46a，46b），并且可以通过Fowler-Nordheim电子隧穿通过相应的隧道氧化物窗（40a，40b）从相应的源区域（30a，30b）。场板导体（40a）控制每个通道区域（38a，38b）内各个子通道区域（70a，70b）的电导。字线或控制栅极导体（62）被绝对地设置在相邻的第三剩余通道子区域（53a，53b）附近，并且还与浮动栅极（46a，46b）绝缘地设置以编程或擦除它们。

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