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1. 发明授权

US5081055A Method of making electrically-erasable, electrically-programmable read-only memory cell having a tunnel window insulator and forming implanted regions for isolation between wordlines 失效
标题翻译：制造具有隧道窗绝缘体并形成用于字线间隔离的注入区域的电可擦除电可编程只读存储单元的方法
公开(公告)号：US5081055A
公开(公告)日：1992-01-14
申请号：US648248
申请日：1991-01-31
申请人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
发明人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L29/7883
摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ration of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between cells in the wordline direction is by a self-aligned implanted region, in this embodiment.
摘要翻译：使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，以无接触电池布局，增强了易于制造和减小电池尺寸。位线和源极/漏极区域被埋在相对厚的氧化硅之下，这允许控制栅极对浮置栅极电容的有利比例。编程和擦除由位于源的通道侧附近或上方的隧道窗口区域提供。窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。在本实施例中，字线方向上的单元之间的隔离是通过自对准注入区域。

2. 发明授权

US5012307A Electrically-erasable, electrically-programmable read-only memory 失效
标题翻译：电可擦除，电可编程只读存储器
公开(公告)号：US5012307A
公开(公告)日：1991-04-30
申请号：US494060
申请日：1990-03-15
申请人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
发明人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L29/7883
摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between wordlines is also by thick thermal oxide in a preferred embodiment, further improving the coupling ratio. Bitline and wordline spacing may be selected for optimum pitch or aspect ratio. Bitline to substrate capacitance is minimized.
摘要翻译：使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了易于制造和减小电池尺寸。位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。隧道窗口提供的编程和擦除靠近或高于源的通道侧。窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。在优选实施例中，字线之间的隔离也是厚氧化物，进一步提高了耦合比。可以选择位线和字线间距来获得最佳间距或宽高比。位线到基板电容最小化。

3. 发明授权

US4823318A Driving circuitry for EEPROM memory cell 失效
标题翻译： EEPROM存储单元的驱动电路
公开(公告)号：US4823318A
公开(公告)日：1989-04-18
申请号：US239877
申请日：1988-09-02
申请人： Sebastiano D'Arrigo , Giuliano Imondi , Sung-Wei Lin , Manzur Gill
发明人： Sebastiano D'Arrigo , Giuliano Imondi , Sung-Wei Lin , Manzur Gill
IPC分类号： G11C17/00 , G11C16/06 , G11C16/08 , G11C16/12 , G11C16/14 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/08 , G11C16/12 , G11C16/14
摘要： A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising four P-channel transistors and two N-channel transistors as well as four switches. The circuit comprises a two-transistor inverter with a feedback transistor and three isolating transistors that prevent excessive currents and voltages from damaging internal and external circuit components.

4. 发明授权

US5017980A Electrically-erasable, electrically-programmable read-only memory cell 失效
标题翻译：电可擦除，电可编程只读存储单元
公开(公告)号：US5017980A
公开(公告)日：1991-05-21
申请号：US494051
申请日：1990-03-15
申请人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
发明人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L29/7883
摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between cells in the wordline direction is by a self-aligned implanted region, in this embodiment.
摘要翻译：使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了易于制造和减小电池尺寸。位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。编程和擦除由位于源的通道侧附近或上方的隧道窗口区域提供。窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。在本实施例中，字线方向上的单元之间的隔离是通过自对准注入区域。

5. 发明授权

US5187683A Method for programming EEPROM memory arrays 失效
标题翻译： EEPROM存储器阵列编程方法
公开(公告)号：US5187683A
公开(公告)日：1993-02-16
申请号：US576307
申请日：1990-08-31
申请人： Manzur Gill , Sung-Wei Lin , Sebastiano D'Arrigo
发明人： Manzur Gill , Sung-Wei Lin , Sebastiano D'Arrigo
IPC分类号： G11C17/00 , G11C16/02 , G11C16/08 , G11C16/10 , H01L21/8247 , H01L27/115
CPC分类号： G11C16/08 , G11C16/10
摘要： A method is described for programming a semiconductor array of EEPROM cells. A selected cell is connected, by definition, to a selected source-column line, a selected drain-column line and a selected wordline. Each deselected memory cell in the array is connected to a deselected source-column line, a deselected drain-column line and/or a deselected wordline. The method includes preselecting first, second, third, fourth and fifth programming voltages such that the second programming voltage is more positive than the first programming voltage and such that the third, fourth and fifth programming voltages are intermediate between the first and second programming voltages. The first programming voltage is applied at least to a selected column line and to each of the same-type deselected column lines. The third programming voltage is applied to the selected wordline and the fourth programming voltage is applied to each deselected wordline. After a pre-charge time interval, the fifth programming voltage is applied to each same-type deselected column line and, after an optional additional pre-charge time interval, the second programming voltage is applied to the selected wordline. After a program time interval, the third programming voltage is applied to the selected wordline and, after an optional discharge time interval, the first programming voltage is applied to each same-type deselected column line. Each deselected wordline is maintained at the fourth programming voltage for an additional discharge time interval. The third, fourth and fifth programming voltages may have the same value.
摘要翻译：描述了一种用于编程EEPROM单元的半导体阵列的方法。根据定义，所选择的单元格连接到所选择的源列行，所选的排列列线和所选择的字线。阵列中的每个取消选择的存储单元连接到未选择的源 - 列线，取消选择的漏 - 列线和/或未选择的字线。该方法包括预选第一，第二，第三，第四和第五编程电压，使得第二编程电压比第一编程电压更正，并且使得第三，第四和第五编程电压在第一和第二编程电压之间。至少将第一编程电压施加到所选择的列线和每个相同类型的未选择的列线。将第三编程电压施加到所选择的字线，并且将第四编程电压施加到每个取消选择的字线。在预充电时间间隔之后，将第五编程电压施加到每个相同类型的未选择的列线，并且在可选的附加预充电时间间隔之后，将第二编程电压施加到所选择的字线。在编程时间间隔之后，将第三编程电压施加到所选择的字线，并且在可选的放电时间间隔之后，将第一编程电压施加到每个相同类型的未选择的列线。每个取消选择的字线保持在第四个编程电压下一个额外的放电时间间隔。第三，第四和第五编程电压可以具有相同的值。

6. 发明授权

US5156991A Fabricating an electrically-erasable, electrically-programmable read-only memory having a tunnel window insulator and thick oxide isolation between wordlines 失效
标题翻译：制造具有隧道窗绝缘体和字线之间的厚氧化物隔离的电可擦除的电可编程只读存储器
公开(公告)号：US5156991A
公开(公告)日：1992-10-20
申请号：US648087
申请日：1991-01-31
申请人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
发明人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L29/7883 , Y10S438/981
摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between wordlines is also by thick thermal oxide in a preferred embodiment, further improving the coupling ratio. Bitline and wordline spacing may be selected for optimum pitch or aspect ratio. Bitline to substrate capacitance is minimized.
摘要翻译：使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了易于制造和减小电池尺寸。位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。隧道窗口提供的编程和擦除靠近或高于源的通道侧。窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。在优选实施例中，字线之间的隔离也是厚氧化物，进一步提高了耦合比。可以选择位线和字线间距来获得最佳间距或宽高比。位线到基板电容最小化。

7. 发明授权

US5177705A Programming of an electrically-erasable, electrically-programmable, read-only memory array 失效
标题翻译：电可擦除，电可编程只读存储器阵列的编程
公开(公告)号：US5177705A
公开(公告)日：1993-01-05
申请号：US402399
申请日：1989-09-05
申请人： David J. McElroy , Sebastiano D'Arrigo , Manzur Gill , Sung-Wei Lin
发明人： David J. McElroy , Sebastiano D'Arrigo , Manzur Gill , Sung-Wei Lin
IPC分类号： G11C16/04 , G11C16/10 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0425 , G11C16/10
摘要： A method is described for programming an array of EEPROM cells. Programming occurs through a Fowler-Nordheim tunnel window (34) between a source bitline (24) and a floating gate conductor (42) of a selected cell. The voltages applied to the control gate and to the source are selected to differ sufficiently to cause electrons to be drawn through the tunnel window (34) from the source region (24) to the floating gate conductor (42). The non-selected bitlines have a voltage impressed thereon that is of sufficient value to prevent inadvertent programming of cells in the selected row. The non-selected wordlines (48) have a voltage impressed thereon that is of sufficient value to prevent erasing of programmed non-selected cells.
摘要翻译：描述了一种用于编程EEPROM单元阵列的方法。编程通过位于选定单元的源位线（24）和浮动栅极导体（42）之间的Fowler-Nordheim隧道窗口（34）进行。选择施加到控制栅极和源极的电压以使其不同以使得电子从源极区域（24）通过隧道窗口（34）从浮动栅极导体（42）拉出。未选择的位线具有施加在其上的电压，其具有足够的值以防止所选行中的单元的无意编程。未选择的字线（48）具有其上施加的电压，其具有足够的值以防止编程的未选择单元的擦除。

8. 发明授权

US5100819A Method of making electrically programmable and erasable memory cells with field plate conductor defined drain regions 失效
标题翻译：制造具有场板导体限定漏极区域的电可编程和可擦除存储单元的方法
公开(公告)号：US5100819A
公开(公告)日：1992-03-31
申请号：US618786
申请日：1990-11-27
申请人： Manzur Gill , Sebastiano D'Arrigo
发明人： Manzur Gill , Sebastiano D'Arrigo
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60a , 60b) to control their conductance. A control gate conductor is insulatively disposed adjacent the control gate subchannel regions (62a, 62b) to control their conductance. In another embodiment, the field plate conductor (100) is replaced with a pair of field plate conductors (42a, 42b) that control the conductance of respective subchannel regions (64a, 64b). The field plate conductors (42a, 42b) act to self-align a diffused drain region (46) that replaces the inversion region (102).
摘要翻译：第一和第二EEPROM单元具有在半导体层（12）中形成为与第一导电类型相反的第二导电类型并且彼此间隔开的第一和第二源极区（28a，28b）。场平板导体（100）被绝缘地邻近并限定反转区域（102），并且还在第一和第二源极区域（28a，28b）之间横向隔开。当对场板导体（100）施加预定电压时，反转区域（102）从第一导电类型转换为第二导电类型。第一和第二通道区域（48a，48b）被限定在各个源极区域（28a + B，28b）和反转区域（102）之间，并且每个包括浮动栅极和控制栅极子通道区域（60a，62a，62b，60b）。第一和第二浮栅导体（40a，40b）被绝缘地设置在相邻的浮栅子通道区域（60a，60b）附近，以控制它们的电导。控制栅极导体与控制栅极子通道区域（62a，62b）相邻地间隔地设置以控制它们的电导。在另一实施例中，场板导体（100）由控制各个子通道区域（64a，64b）的电导的一对场板导体（42a，42b）代替。场板导体（42a，42b）用于使取代反转区域（102）的扩散漏极区域（46）自对准。

9. 发明授权

US4947222A Electrically programmable and erasable memory cells with field plate conductor defined drain regions 失效
标题翻译：电气可编程和可擦除存储单元，具有定义漏极区域的导体板导体
公开(公告)号：US4947222A
公开(公告)日：1990-08-07
申请号：US385846
申请日：1989-07-26
申请人： Manzur Gill , Sebastiano D'Arrigo
发明人： Manzur Gill , Sebastiano D'Arrigo
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a, 28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60 a, 60b) to control their conductance. A control gate conductor is insulatively disposed adjacent the control gate subchannel regions (62a, 62b) to control their conductance. In another embodiment, the floating gate conductor (100) is replaced with a pair of field plate conductors (42a, 42b) that control the conductance of respective subchannel regions (64a, 64b). The field plate conductors (42a, 42b) act to self-align a diffused drain region (46) that replaces the inversion region (102).
摘要翻译：第一和第二EEPROM单元具有在半导体层（12）中形成为与第一导电类型相反的第二导电类型并且彼此间隔开的第一和第二源极区（28a，28b）。场平板导体（100）被绝缘地邻近并限定反转区域（102），并且还在第一和第二源极区域（28a，28b）之间横向隔开。当对场板导体（100）施加预定电压时，反转区域（102）从第一导电类型转换为第二导电类型。第一和第二通道区域（48a，48b）被限定在各个源极区域（28a，28b）和反转区域（102）之间，并且各自包括浮动栅极和控制栅极子通道区域（60a，62a，62b，60b）。第一和第二浮栅导体（40a，40b）被绝缘地设置在相邻的浮栅子通道区域（60a，60b）附近，以控制它们的电导。控制栅极导体与控制栅极子通道区域（62a，62b）相邻地间隔地设置以控制它们的电导。在另一个实施例中，浮动栅极导体（100）由控制各个子通道区域（64a，64b）的电导的一对场板导体（42a，42b）代替。场板导体（42a，42b）用于使取代反转区域（102）的扩散漏极区域（46）自对准。

10. 发明授权

US5173436A Method of manufacturing an EEPROM with trench-isolated bitlines 失效
标题翻译：制造具有沟槽隔离位线的EEPROM的方法
公开(公告)号：US5173436A
公开(公告)日：1992-12-22
申请号：US722732
申请日：1991-06-27
申请人： Manzur Gill , Sebastiano D'Arrigo , David J. McElroy
发明人： Manzur Gill , Sebastiano D'Arrigo , David J. McElroy
IPC分类号： H01L21/28 , H01L21/762 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11517 , H01L21/28273 , H01L21/76202 , H01L27/115 , H01L29/7883
摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using a floating-gate transistor with or without a split gate. The floating-gate transistor may have a self-aligned tunnel window of sublithographic dimension positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide and the floating gate extends over the thick silicon oxide. Programming and erasing are accomplished by causing electrons to tunnel through the oxide in the tunnel window. The tunnel window has a thinner dielectric than the remainder of the oxides under the floating gate to allow Fowler-Nordheim tunneling. Trenches and ditches are used for electrical isolation between individual memory cells, allowing an increase in cell density.
摘要翻译：使用具有或不具有分裂栅极的浮栅晶体管构造电可擦除的电可编程ROM或EEPROM。浮栅晶体管可以具有位于与源极和漏极相反侧的亚光刻尺寸的自对准隧道窗口，在无接触电池布局中，增强了制造的容易性并减小了单元尺寸。在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，并且浮置栅极延伸在厚的氧化硅上。通过使电子穿过隧道窗中的氧化物来实现编程和擦除。隧道窗口的电介质比浮动栅极下方的氧化物的电介质薄，以允许Fowler-Nordheim隧道。沟槽和沟渠用于各个记忆体之间的电隔离，允许增加细胞密度。

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