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41. 发明授权

US4224564A Statistical enhancement of the accuracy of a ratio-matched network in a circuit chip 失效
标题翻译：统计增强电路芯片中比例匹配网络的精度
公开(公告)号：US4224564A
公开(公告)日：1980-09-23
申请号：US911463
申请日：1978-06-01
申请人： Robert C. Dobkin , James B. Cecil , Joseph J. Connolly, Jr.
发明人： Robert C. Dobkin , James B. Cecil , Joseph J. Connolly, Jr.
IPC分类号： H03M1/00 , G05F3/00
CPC分类号： H03M1/785
摘要： A statistically enhanced ratio-matched network in a circuit chip is disclosed. The network may be either a resistance network or a capacitance network. In a ratio-matched resistance network, such as an R-2R resistance ladder, a plurality of resistances in a circuit chip have a rational ratio of resistance values to each other. All of the resistances each consists of an integral number of simultaneously fabricated resistors of approximately uniform dimensions, and certain critical resistances each consists of a series-parallel combination of the resistors for statistically enhancing the accuracy of the rational ratio of the critical resistances to each other.
摘要翻译：公开了一种在电路芯片中统计增强的比匹配网络。网络可以是电阻网络或电容网络。在诸如R-2R电阻梯的比匹配电阻网络中，电路芯片中的多个电阻具有彼此的电阻值的合理比率。所有电阻各自由大致均匀尺寸的整体数量的同时制造的电阻组成，并且某些关键电阻各自由电阻器的串联并联组合组成，用于统计提高临界电阻相互之间的有理比的精度。

42. 发明授权

US08378657B2 Paralleling voltage regulators 有权
公开(公告)号：US08378657B2
公开(公告)日：2013-02-19
申请号：US12541557
申请日：2009-08-14
申请人： Robert C. Dobkin
发明人： Robert C. Dobkin
IPC分类号： G05F3/10 , G05F1/567
CPC分类号： G05F1/46 , H02J1/10 , Y10S323/907 , Y10T307/565
摘要： Circuits and methods for paralleling voltage regulators are provided. Improved current sharing and regulation characteristics are obtained by coupling control terminals of the voltage regulators together which results in precise output voltages and proportional current production. Distributing current generation among multiple paralleled voltage regulators improves heat dissipation and thereby reduces the likelihood that the current produced by the voltage regulators will be temperature limited.

43. 发明授权

US08085029B2 Bandgap voltage and current reference 有权
标题翻译：带隙电压和电流参考
公开(公告)号：US08085029B2
公开(公告)日：2011-12-27
申请号：US11731279
申请日：2007-03-30
申请人： Robert C. Dobkin
发明人： Robert C. Dobkin
IPC分类号： G05F3/16 , G05F3/20
CPC分类号： G05F3/30
摘要： Circuits and methods that improve the performance of reference circuits are provided. A reference generator circuit maintains a substantially constant output current over an extended temperature for use as a reference. Output current fluctuations caused by a poorly specified power source or process variations are minimized or eliminated.
摘要翻译：提供了提高参考电路性能的电路和方法。参考发生器电路在扩展温度下保持基本恒定的输出电流，以用作参考。由指定的电源或工艺变化引起的输出电流波动被最小化或消除。

44. 发明授权

US07414473B1 Class AB folded-cascode amplifier having cascode compensation 有权
标题翻译： AB类折叠共源共栅放大器，具有共源共栅补偿
公开(公告)号：US07414473B1
公开(公告)日：2008-08-19
申请号：US11493654
申请日：2006-07-27
申请人： Surapap Rayanakorn , Robert C. Dobkin , Brendan J. Whelan
发明人： Surapap Rayanakorn , Robert C. Dobkin , Brendan J. Whelan
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F1/483 , H03F3/3022 , H03F2200/36 , H03F2200/513 , H03F2203/30033 , H03F2203/45302 , H03F2203/45512
摘要： A class AB folded-cascode amplifier having improved gain-bandwidth product, comprises a differential input circuit including a differential transistor pair coupled to a source of tail current and responsive to a differential input signal for conducting a first current, a cascode circuit coupled to the differential input circuit for supplying a second current thereto, and a class AB output stage. A compensation circuit is configured for feeding back mutually complementary compensation signals from an output node to the differential input circuit.
摘要翻译：具有改进的增益带宽乘积的AB类折叠共源共栅放大器包括差分输入电路，差分输入电路包括耦合到尾电流源的差分晶体管对，并响应用于传导第一电流的差分输入信号，耦合到用于提供第二电流的差分输入电路和AB类输出级。补偿电路被配置为将相互补偿的补偿信号从输出节点反馈到差分输入电路。

45. 发明授权

US06518733B1 Circuits and techniques for capacitor charging circuits 有权
公开(公告)号：US06518733B1
公开(公告)日：2003-02-11
申请号：US09921466
申请日：2001-08-03
申请人： Jeffrey Schenkel , Albert M. Wu , Robert C. Dobkin , Steven M. Pietkiewicz
发明人： Jeffrey Schenkel , Albert M. Wu , Robert C. Dobkin , Steven M. Pietkiewicz
IPC分类号： H02J700
CPC分类号： H05B41/30 , H02M3/33507
摘要： The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

46. 发明授权

US5945728A Lead frame capacitor and capacitively coupled isolator circuit 失效
标题翻译：引线框电容和电容耦合隔离电路
公开(公告)号：US5945728A
公开(公告)日：1999-08-31
申请号：US807197
申请日：1997-02-27
申请人： Robert C. Dobkin , Robert L. Reay
发明人： Robert C. Dobkin , Robert L. Reay
IPC分类号： H01L23/50 , H01L21/822 , H01L23/495 , H01L23/64 , H01L25/00 , H01L27/04 , H05K1/16 , H05K3/20 , H01L23/28
CPC分类号： H01L23/49575 , H01L23/49589 , H01L23/642 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01014 , H01L2924/14 , H01L2924/19041 , H05K1/162 , H05K3/202 , Y10S257/904 , Y10T29/435
摘要： A capacitor is provided including first and second electrodes formed from portions of the lead frame structure used in conventional integrated circuit packaging. The electrodes are encapsulated with dielectric molding material which provides dielectric insulation between the electrodes. A low power capacitively-coupled digital isolator circuit is also provided. The circuit employs a pair of the lead frame capacitors of the present invention and includes differential driver and receiver circuits. The receiver can also include an optional filter for increasing noise and glitch immunity.
摘要翻译：提供一种电容器，包括由常规集成电路封装中使用的引线框架结构的部分形成的第一和第二电极。电极用介电模塑材料封装，其在电极之间提供介电绝缘。还提供了一种低功率电容耦合数字隔离电路。该电路采用本发明的一对引线框电容器，并包括差分驱动器和接收器电路。接收机还可以包括可选的滤波器，以增加噪声和毛刺抗扰度。

47. 发明授权

US5148118A Level shift circuit with gain enhancement 失效
标题翻译：具有增益增益的电平移位电路
公开(公告)号：US5148118A
公开(公告)日：1992-09-15
申请号：US673475
申请日：1991-03-22
申请人： Robert C. Dobkin , John W. Wright
发明人： Robert C. Dobkin , John W. Wright
IPC分类号： H03F3/45 , H03F3/50
CPC分类号： H03F3/45071 , H03F3/50
摘要： A new level shifting circuit is presented which does not restrict the upper limit of the common-mode input range of an operational amplifier. This is important particularly in operational amplifiers designated to operate with low power supply voltages. Significant parameters. of the operational amplifier, such as the gain and the slew rate, can be controlled without adversely affecting the common-mode input voltage range. The level shifting stage operates nondifferentially to avoid stability problems found in differential stages. A further improvement is accomplished using current balancing to achieve gain enhancement.
摘要翻译：提出了一种不限制运算放大器的共模输入范围的上限的新的电平移位电路。特别是在指定用低电源电压工作的运算放大器时，这一点非常重要。重要参数可以控制诸如增益和转换速率的运算放大器，而不会对共模输入电压范围产生不利影响。电平转换阶段非周期地运行，以避免在差分阶段发现的稳定性问题。使用电流平衡来实现进一步的改进以实现增益增强。

48. 发明授权

US4988952A High Q switched capacitor filter having internal thin-film resistors 失效
标题翻译：高Q开关电容滤波器具有内部薄膜电阻
公开(公告)号：US4988952A
公开(公告)日：1991-01-29
申请号：US362144
申请日：1989-06-06
申请人： Nello G. Sevastopoulos , Robert C. Dobkin
发明人： Nello G. Sevastopoulos , Robert C. Dobkin
IPC分类号： H03H19/00
CPC分类号： H03H19/004
摘要： Disclosed is a switched capacitor filter block having a nonlinear quality coefficient, Q, whereby quality can be enhanced while limiting the size of feedback resistors in the filter block. A pair of capacitors alternately switchably connect an input signal to the input of integrator whereby the sampling frequency is twice the switching frequency. The filter block is readily fabricated in a monolithic integrated circuit with the feedback resistors being thin-film resistors formed on the surface of the monolithic integrated circuit. Such a circuit configuration is more accurate in programming and requires only one mask step in fabrication to program.
摘要翻译：公开了具有非线性质量系数Q的开关电容滤波器块，由此可以在限制滤波器块中的反馈电阻器的尺寸的同时提高质量。一对电容器交替地将输入信号连接到积分器的输入，由此采样频率是开关频率的两倍。滤波器块容易地制造在单片集成电路中，反馈电阻器是形成在单片集成电路的表面上的薄膜电阻器。这样的电路配置在编程中更准确，并且在制造中仅需要一个掩模步骤来编程。

49. 发明授权

US4410839A Apparatus for controlling power consumption in lighting loads and the like 失效
标题翻译：用于控制照明负载中的功率消耗的装置等
公开(公告)号：US4410839A
公开(公告)日：1983-10-18
申请号：US279775
申请日：1981-07-02
申请人： Robert C. Dobkin
发明人： Robert C. Dobkin
IPC分类号： H02M5/257 , H03K17/725 , H03K17/735 , H05B37/00
CPC分类号： H02M5/2573 , H03K17/725 , H03K17/735 , Y10T307/957
摘要： Apparatus for interrupting power to a plurality of parallel loads such as lighting circuits and selectively reapplying power to the loads includes a first switch serially interconnecting the loads to a power line. Second switch circuits are serially connected with each load whereby interruption of power to a load for a predetermined period of time opens the switch circuits. The switch circuits include bidirectional conduction devices such as triacs which require a gating signal before becoming conductive. A resistor-capacitor circuit provides a gating signal to the triac to maintain conduction thereof for the predetermined period of time.
摘要翻译：用于中断对诸如照明电路的多个并联负载的功率并且选择性地重新施加电力到负载的装置包括将负载串联连接到电力线的第一开关。第二开关电路与每个负载串联连接，从而在一段预定的时间段内断开负载电源以打开开关电路。开关电路包括双向传导器件，例如在变成导通之前需要门控信号的三端双向可控硅开关元件。电阻电容电路向三端双向可控硅开关提供门控信号，以保持其预定时间的导通。

50. 发明授权

US4371792A High gain composite transistor 失效
标题翻译：高增益复合晶体管
公开(公告)号：US4371792A
公开(公告)日：1983-02-01
申请号：US171778
申请日：1980-07-24
申请人： Robert C. Dobkin
发明人： Robert C. Dobkin
IPC分类号： H01L27/082 , H03K17/60 , H01L27/02 , H03K3/26
CPC分类号： H03K17/602 , H01L27/0821
摘要： A composite transistor suitable for use in monolithic integrated circuits is characterized as having extremely high current gain, stable operation and low leakage current. Two vertical NPN transistors are coupled into a circuit configuration, along with two lateral PNP transistors, that has three terminals. These terminals behave as a single NPN transistor having characteristics that are superior to those of a conventional NPN transistor.
摘要翻译：适用于单片集成电路的复合晶体管的特征在于具有极高的电流增益，稳定的工作和低的漏电流。两个垂直NPN晶体管连接到具有三个端子的两个侧向PNP晶体管的电路配置中。这些端子表现为具有优于常规NPN晶体管的特性的单个NPN晶体管。

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