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41. 发明授权

US07366036B2 Memory device with control circuit for regulating power supply voltage 失效
标题翻译：具有用于调节电源电压的控制电路的存储器件
公开(公告)号：US07366036B2
公开(公告)日：2008-04-29
申请号：US11331618
申请日：2006-01-13
申请人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
发明人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/148
摘要： A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.
摘要翻译：本地动态功率控制器（LDPC）产生负载全摆幅电压信号和降低的摆幅电压电源信号。全电源和降压电源都是从单个电源产生的。当负载处于完全工作模式时，提供全摆幅电压供应信号，而当负载处于睡眠模式时提供降压电压信号。因此，减少了在负载中消耗的功率。

42. 发明申请

US20080082882A1 DOUBLE-EDGE TRIGGERED SCANNABLE PULSED FLIP-FLOP FOR HIGH FREQUENCY AND/OR LOW POWER APPLICATIONS 审中-公开
标题翻译：用于高频和/或低功率应用的双边触发扫描脉冲FLIP-FLOP
公开(公告)号：US20080082882A1
公开(公告)日：2008-04-03
申请号：US11531310
申请日：2006-09-13
申请人： Christopher M. Durham , Jenny Fan , Peter J. Klim , Robert N. Krentler
发明人： Christopher M. Durham , Jenny Fan , Peter J. Klim , Robert N. Krentler
IPC分类号： G01R31/28
CPC分类号： G01R31/318575 , G01R31/318502 , G01R31/318541
摘要： A circuit for data storage is presented. The circuit includes clock generation circuits for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock and first and second scan clock signals. The circuit further includes a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, and a scan input and a scan output that are also connected with the internal storage node. In a function mode of operation, the first and second scan clock signals are held at a logic level to allow data to pass from the data input to the internal storage node at the first clock pulse and from the internal storage node to the data output at the second clock pulse signal. In a scan mode of operation the pulse clock signal is held at a logic level to allow data to pass from the scan input to the internal storage node at a pulse of the first scan clock signal and from the internal storage node to the scan output at a pulse of the second scan clock signal.
摘要翻译：介绍了一种用于数据存储的电路。电路包括用于产生具有用于系统时钟的每个时钟周期的第一和第二时钟脉冲和第一和第二扫描时钟信号的脉冲时钟信号的时钟产生电路。电路还包括具有与内部存储节点连接的数据输入和数据输出以及也与内部存储节点连接的扫描输入和扫描输出的可扫描脉冲触发器电路。在功能操作模式中，第一和第二扫描时钟信号被保持在逻辑电平，以允许数据在第一时钟脉冲从数据输入到内部存储节点并从内部存储节点传递到数据输出第二个时钟脉冲信号。在扫描操作模式中，脉冲时钟信号保持在逻辑电平，以允许数据以第一扫描时钟信号的脉冲从扫描输入传递到内部存储节点，并且从内部存储节点到扫描输出第二扫描时钟信号的脉冲。

43. 发明申请

US20080016475A1 Method, System and Program Product for Automated Transistor Tuning in an Integrated Circuit Design 审中-公开
标题翻译：集成电路设计中自动晶体管调谐的方法，系统和程序产品
公开(公告)号：US20080016475A1
公开(公告)日：2008-01-17
申请号：US11457332
申请日：2006-07-13
申请人： Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
发明人： Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
IPC分类号： G06F17/50
CPC分类号： G06F17/5063
摘要： A method of tuning an integrated circuit design includes holding a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizing transistors forming a register within the integrated circuit design and thereafter optimizing transistors forming one or more clock buffers coupled to the reference clock signal.
摘要翻译：调整集成电路设计的方法包括在集成电路设计中保持参考时钟信号恒定，并且当参考时钟信号保持不变时，优化在集成电路设计内形成寄存器的晶体管，然后优化形成一个或多个时钟的晶体管耦合到参考时钟信号的缓冲器。

44. 发明授权

US06785847B1 Soft error detection in high speed microprocessors 失效
标题翻译：高速微处理器软错误检测
公开(公告)号：US06785847B1
公开(公告)日：2004-08-31
申请号：US09631714
申请日：2000-08-03
申请人： Paul J. Jordan , Peter J. Klim
发明人： Paul J. Jordan , Peter J. Klim
IPC分类号： G06F1100
CPC分类号： G06F11/1695 , G06F11/1637
摘要： Aspects for soft error detection for a superscalar microprocessor are described. The aspects include a first pipeline, the first pipeline including a first arithmetic logic unit, ALU, comparator and a first general purpose register, GPR, for storing first data, and a second pipeline, the second pipeline including a second GPR and a second ALU comparator, the second GPR for storing second data, the second data being a copy of the first data. A detection system utilizes one of the first and second ALU comparators to perform a comparison of the second data with the first data during an idle state of the first and second pipelines.
摘要翻译：对超标量微处理器的软错误检测方面进行了说明。所述方面包括第一流水线，所述第一流水线包括第一算术逻辑单元ALU比较器和用于存储第一数据的第一通用寄存器GPR和第二流水线，所述第二流水线包括第二GPR和第二ALU 比较器，用于存储第二数据的第二GPR，第二数据是第一数据的副本。检测系统利用第一和第二ALU比较器中的一个，在第一和第二管道的空闲状态期间执行第二数据与第一数据的比较。

45. 发明授权

US6133758A Selectable self-timed replacement for self-resetting circuitry 失效
标题翻译：自复位电路可选择自定时更换
公开(公告)号：US6133758A
公开(公告)日：2000-10-17
申请号：US86737
申请日：1998-05-29
申请人： Christopher McCall Durham , Peter J. Klim
发明人： Christopher McCall Durham , Peter J. Klim
IPC分类号： G06F9/38 , H03K19/096 , H03K19/00
CPC分类号： H03K19/0966 , G06F9/3869
摘要： A method and apparatus is provided for changing a self-timed circuit into a self-resetting circuit to reduce the inherent delay of the self-timed circuit by an amount of latency between the assertion of the data and the assertion of the valid signal. Circuitry is provided to enable the effective de-coupling of the self-timing operation to enable data to move through the logic circuitry without the latency associated with the reception and generation of "valid" and "complete" signals being necessary. On the "receiving" side (the circuit being set into self-resetting mode), the logic circuit does not have to wait for the reception of the "valid" signals to begin operation. On the "driving" side (the circuit sending the data), the logic circuit does not have to wait for the "completion" signal to arrive to permit a new operation to occur.
摘要翻译：提供了一种方法和装置，用于将自定时电路改变为自复位电路，以便将自定时电路的固有延迟减小在数据的断言和有效信号的断言之间的等待时间量。提供电路以实现自定时操作的有效解耦，使得数据能够通过逻辑电路移动，而不需要与接收相关联的等待时间并产生“有效”和“完整”信号。在“接收”侧（电路被设置为自复位模式）中，逻辑电路不必等待接收“有效”信号开始运行。在“驱动”侧（发送数据的电路）中，逻辑电路不必等待“完成”信号到达以允许发生新的操作。

46. 发明授权

US5565798A Self-timed control circuit for self-resetting logic circuitry 失效
标题翻译：用于自复位逻辑电路的自定时控制电路
公开(公告)号：US5565798A
公开(公告)日：1996-10-15
申请号：US517224
申请日：1995-08-21
申请人： Christopher M. Durham , Peter J. Klim
发明人： Christopher M. Durham , Peter J. Klim
IPC分类号： H03K19/177 , H03K19/00
CPC分类号： H03K19/17704
摘要： A self-timed control circuit for self-resetting CMOS logic circuitry provides handshaking between macros to ensure that all data inputted to a particular macro is maintained by the source macros until all data inputs have been received. A data output signal from a macro is maintained until the macro receives a complete signal from all receiving macros indicating that the receiving macros have received all data inputs supplied to them.
摘要翻译：用于自复位CMOS逻辑电路的自定时控制电路提供宏之间的握手，以确保输入到特定宏的所有数据由源宏维持，直到接收到所有数据输入。来自宏的数据输出信号被保持，直到宏从所有接收宏接收到完整信号，指示接收宏已经接收到提供给它们的所有数据输入。

47. 发明授权

US5235602A Synchronous/asynchronous I/O channel check and parity check detector 失效
标题翻译：同步/异步I / O通道检查和奇偶校验检测器
公开(公告)号：US5235602A
公开(公告)日：1993-08-10
申请号：US714127
申请日：1991-06-11
申请人： Peter J. Klim
发明人： Peter J. Klim
IPC分类号： G06F11/10 , G06F13/00 , H04L1/00
CPC分类号： G06F11/10
摘要： An improved I/O channel check and parity check detector includes two similar detection paths each of which includes a check detector, a glitch reject circuit, and a read back register. A memory parity error causes a bit to be set in the read back register. An I/O channel check sets another bit in a read back register provided a memory parity error has not been signalled. If such signal occurs, the channel check is rejected. The read back bits are read through a port allowing the system to determine the source of error.

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