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41. 发明授权

US07610472B2 Performing variable and/or bitwise shift operation for a shift instruction that does not provide a variable or bitwise shift option 有权
标题翻译：对不提供可变或位移选项的换档指令执行可变和/或逐位移位操作
公开(公告)号：US07610472B2
公开(公告)日：2009-10-27
申请号：US11422325
申请日：2006-06-05
申请人： Hyeonkuk Jeong , Paul Chang
发明人： Hyeonkuk Jeong , Paul Chang
IPC分类号： G06F9/315
CPC分类号： G06F5/01 , G06F9/30032 , G06F9/3017
摘要： Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The method simulates a shift instruction that shifts an operand by a shift count. The method identifies a first shift command and a second shift command. The method computes a mask value. The mask value depends on whether the shift count is less than half of the operand size or greater than or equal to half of the operand size. The method uses the mask value to cause one of the first shift command and the second shift command to produce no shift. In some embodiments, the method allows for the shift count to be specified in bytes or in bits.
摘要翻译：一些实施例提出了执行可变移位操作的方法。该方法可以由微处理器使用，该微处理器不允许某些操作数大小进行可变移位操作。该方法模拟一个将一个操作数移位一个移位计数的移位指令。该方法识别第一移位指令和第二移位指令。该方法计算一个掩码值。掩码值取决于移位计数是否小于操作数大小的一半，或大于或等于操作数大小的一半。该方法使用掩模值使第一移位指令和第二移位指令之一产生无移位。在一些实施例中，该方法允许以字节或位指定移位计数。

42. 发明申请

US20090245961A1 MACHINING APPARATUS 有权
标题翻译：加工设备
公开(公告)号：US20090245961A1
公开(公告)日：2009-10-01
申请号：US12060460
申请日：2008-04-01
申请人： Paul Chang , Tsair-Rong Chen , Jeen-Sheen Row , Yuan-Fu Tsai
发明人： Paul Chang , Tsair-Rong Chen , Jeen-Sheen Row , Yuan-Fu Tsai
IPC分类号： B23C9/00
CPC分类号： B23C1/002 , B23Q1/66 , Y10T409/305264 , Y10T409/308288 , Y10T409/309576
摘要： A machining apparatus includes a support frame, first and second workbenches, and a tool-mounting unit. The support frame includes a first horizontal frame part, and a second horizontal frame part disposed above the first horizontal frame part. The first and second workbenches are mounted slidably on the first horizontal frame part of the support frame, and is slidable relative to the support frame in a first horizontal direction. The tool-mounting unit is mounted slidably on the second horizontal frame part of the support frame, and is slidable relative to the support frame in a second horizontal direction transverse to the first horizontal direction.
摘要翻译：一种加工装置，包括支撑框架，第一和第二工作台以及工具安装单元。支撑框架包括第一水平框架部分和设置在第一水平框架部分上方的第二水平框架部分。第一和第二工作台可滑动地安装在支撑框架的第一水平框架部分上，并且可在第一水平方向上相对于支撑框架滑动。工具安装单元可滑动地安装在支撑框架的第二水平框架部分上，并且能够在横向于第一水平方向的第二水平方向上相对于支撑框架滑动。

43. 发明申请

US20080136503A1 METHOD AND SYSTEM FOR A PROCESS SENSOR TO COMPENSATE SOC PARAMETERS IN THE PRESENCE OF IC PROCESS MANUFACTURING VARIATIONS 失效
标题翻译：用于在IC工艺制造变化中存在的方法和系统用于补偿SOC参数的过程传感器
公开(公告)号：US20080136503A1
公开(公告)日：2008-06-12
申请号：US11618900
申请日：2006-12-31
申请人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
发明人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
IPC分类号： G05F3/02
CPC分类号： H03F3/45475 , H03F2203/45048
摘要： Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.
摘要翻译：公开了用于在存在IC工艺制造变化的情况下补偿SoC参数的工艺传感器的方法和系统的某些方面。一种方法的方面可以包括确定与单个集成电路内的至少一个晶体管相关联的工艺变化量。可以通过利用与工艺相关的电流，带隙电流和与晶体管的当前温度相关联的电流来补偿确定的工艺变化量。过程相关电流，带隙电流和与晶体管的当前温度相关联的电流可以被组合以产生输出电流。可以基于产生的输出电流来确定可变电阻器两端产生的电压。

44. 发明申请

US20070246794A1 Integrated circuit including power diode 有权
标题翻译：集成电路包括功率二极管
公开(公告)号：US20070246794A1
公开(公告)日：2007-10-25
申请号：US11821234
申请日：2007-06-22
申请人： Paul Chang , Geeng-Chuan Chern , Prognyan Ghosh , Wayne Hsueh , Vladimir Rodov
发明人： Paul Chang , Geeng-Chuan Chern , Prognyan Ghosh , Wayne Hsueh , Vladimir Rodov
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L27/0629 , H01L29/0692 , H01L29/78 , H01L29/861
摘要： A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.
摘要翻译：一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管半导体衬底。介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

45. 发明授权

US07250668B2 Integrated circuit including power diode 有权
公开(公告)号：US07250668B2
公开(公告)日：2007-07-31
申请号：US11040180
申请日：2005-01-20
申请人： Paul Chang , Geeng-Chuan Chern , Prognyan Ghosh , Wayne Y. W. Hsueh , Vladimir Rodov
发明人： Paul Chang , Geeng-Chuan Chern , Prognyan Ghosh , Wayne Y. W. Hsueh , Vladimir Rodov
IPC分类号： H01L29/00
CPC分类号： H01L27/0629 , H01L29/0692 , H01L29/78 , H01L29/861
摘要： A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

46. 发明申请

US20060157815A1 Integrated circuit including power diode 有权
标题翻译：集成电路包括功率二极管
公开(公告)号：US20060157815A1
公开(公告)日：2006-07-20
申请号：US11040180
申请日：2005-01-20
申请人： Paul Chang , Geeng-Chuan Chern , Prognyan Ghosh , Wayne Hsueh , Vladimir Rodov
发明人： Paul Chang , Geeng-Chuan Chern , Prognyan Ghosh , Wayne Hsueh , Vladimir Rodov
IPC分类号： H01L29/00
CPC分类号： H01L27/0629 , H01L29/0692 , H01L29/78 , H01L29/861
摘要： A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.
摘要翻译：一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管半导体衬底。介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

47. 发明申请

US20050232159A1 Scalable extensible network test architecture 失效
公开(公告)号：US20050232159A1
公开(公告)日：2005-10-20
申请号：US11133073
申请日：2005-05-18
申请人： Jeong Joo , Fred King , Patrick Riley , Aart Konynenberg , Paul Chang
发明人： Jeong Joo , Fred King , Patrick Riley , Aart Konynenberg , Paul Chang
IPC分类号： G06F1/26 , H04L1/00
CPC分类号： G06F1/189 , G06F1/181 , H04L43/50
摘要： A network test architecture includes a plurality of modules for performing a plurality of functions, each of the plurality of modules having a unique identifier. An additional module for performing an additional function has an additional unique identifier. A control bus is connected among the plurality of modules; a data bus is connected among the plurality of modules; and a power bus is connected among the plurality of modules. A controller controls operation, data transmission, and powering of the plurality of modules and the additional module, respectively, through the control bus, the data bus, and the power bus, the controller using the unique identifier and the additional unique identifier of the plurality of modules upon simultaneous connection of the control bus, the data bus, and the power bus to the additional module.

48. 发明授权

US06624030B2 Method of fabricating power rectifier device having a laterally graded P-N junction for a channel region 有权
标题翻译：制造具有用于沟道区域的横向渐变的P-N结的功率整流装置的方法
公开(公告)号：US06624030B2
公开(公告)日：2003-09-23
申请号：US09742262
申请日：2000-12-19
申请人： Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Vladimir Rodov , Charles Lin
发明人： Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Vladimir Rodov , Charles Lin
IPC分类号： H01L21336
CPC分类号： H01L29/861 , H01L21/2815 , H01L29/0696 , H01L29/6609 , H01L29/7802
摘要： A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction separating the channel region from the substrate of first conductivity type. In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.
摘要翻译：一种垂直半导体整流器件包括第一导电类型的半导体衬底，并且具有绝缘地形成在第一主表面上的多个栅极和在第一导电类型的第一导电类型的表面区域中形成的多个第一导电类型的源极/漏极区域主要表面毗邻门。第二导电类型的多个通道每个都邻接源极/漏极区并在栅极下方延伸，每个沟道横向渐变，其中沟道区域与第一导电类型的衬底分离出倾斜的P-N结。在制造垂直半导体整流器件时，在半导体表面上形成一个部分离子掩模，该掩模具有倾斜表面，该倾斜表面改变通过该掩模的离子的路径长度以形成横向渐变的沟道区。

49. 发明授权

US06579144B1 Method of manufacturing environmental protective paper doll 失效
标题翻译：环保纸娃娃制作方法
公开(公告)号：US06579144B1
公开(公告)日：2003-06-17
申请号：US10189002
申请日：2002-07-05
申请人： Paul Chang
发明人： Paul Chang
IPC分类号： A63H300
CPC分类号： A63H9/00
摘要： A method of manufacturing an environmental protective paper doll includes the steps of using recycle paper as the manufacturing material; adding appropriate proportion of water to the paper pulp after a slight filtering to make a paste; pressing the vacuum mold on the protruded mold plate after tying the net; submerging in a trough containing the pasty paper pulp; drawing out the liquid in the vacuum shaping mold to facilitate the formation of an embryo layer with appropriate thickness on the tying net of the protrusion member; engaging the upper mold and the lower mold together and preliminarily removing the water content; baking the semi-finished embryo layer for dehydration; pasting the front and rear halves with glue; trimming the rough edge and coating the paper surface with a layer of golden paint to increase the hardness of the surface; and then painting with the stylish colors and forming the paper doll.
摘要翻译：制造环保纸娃娃的方法包括以回收纸作为制造材料的步骤; 在轻轻过滤后加入适量的水分至纸浆中制成糊状物; 扣网后将真空模压在突出模板上; 浸没在含有糊状纸浆的槽中; 抽出真空成型模具中的液体，以便在突出部件的网状网上形成适当厚度的胚层; 将上模和下模结合在一起并预先除去含水量; 烘干半成品胚层脱水; 用胶水粘贴前后两半; 修剪粗糙的边缘，并用一层金色涂料涂覆纸张表面以增加表面的硬度; 然后用时尚的颜色绘画并形成纸娃娃。

50. 发明授权

US06515330B1 Power device having vertical current path with enhanced pinch-off for current limiting 失效
标题翻译：具有垂直电流路径的功率器件，具有增强的夹断电流限制
公开(公告)号：US06515330B1
公开(公告)日：2003-02-04
申请号：US10037495
申请日：2002-01-02
申请人： Gary M. Hurtz , Vladimir Rodov , Geeng-Chuan Chern , Paul Chang , Ching-Lang Chiang
发明人： Gary M. Hurtz , Vladimir Rodov , Geeng-Chuan Chern , Paul Chang , Ching-Lang Chiang
IPC分类号： H01L2976
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/1095 , H01L29/66712 , H01L29/7802 , H01L29/861
摘要： A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain terminal as the cathode. The doping profile of the body is so tailored with ion implantation that a depletion region pinches off to limit current. The body comprises a shallow implant to form a MOS channel and an additional deep implant through a spacer shielding the channel area. Implanted a higher energies and at an acute angle, the deep implant protrudes into the regular current path of the vertical MOSFET.
摘要翻译：半导体限流器件由两端垂直N（P）沟道MOSFET器件提供，其栅极，体和源极端子连接在一起作为阳极，漏极端子作为阴极。使用离子注入来定制主体的掺杂特性，耗尽区夹紧以限制电流。主体包括浅植入物以形成MOS通道，并通过隔离屏蔽通道区域的间隔物进行额外的深度注入。注入较高的能量并且以锐角，深的注入突出到垂直MOSFET的常规电流通路中。

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