专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080136503A1 METHOD AND SYSTEM FOR A PROCESS SENSOR TO COMPENSATE SOC PARAMETERS IN THE PRESENCE OF IC PROCESS MANUFACTURING VARIATIONS 失效
标题翻译：用于在IC工艺制造变化中存在的方法和系统用于补偿SOC参数的过程传感器
公开(公告)号：US20080136503A1
公开(公告)日：2008-06-12
申请号：US11618900
申请日：2006-12-31
申请人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
发明人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
IPC分类号： G05F3/02
CPC分类号： H03F3/45475 , H03F2203/45048
摘要： Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.
摘要翻译：公开了用于在存在IC工艺制造变化的情况下补偿SoC参数的工艺传感器的方法和系统的某些方面。一种方法的方面可以包括确定与单个集成电路内的至少一个晶体管相关联的工艺变化量。可以通过利用与工艺相关的电流，带隙电流和与晶体管的当前温度相关联的电流来补偿确定的工艺变化量。过程相关电流，带隙电流和与晶体管的当前温度相关联的电流可以被组合以产生输出电流。可以基于产生的输出电流来确定可变电阻器两端产生的电压。

2. 发明授权

US08237492B2 Method and system for a process sensor to compensate SOC parameters in the presence of IC process manufacturing variations 失效
标题翻译：用于在存在IC工艺制造变化的情况下补偿SOC参数的过程传感器的方法和系统
公开(公告)号：US08237492B2
公开(公告)日：2012-08-07
申请号：US11618900
申请日：2006-12-31
申请人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
发明人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
IPC分类号： G05F3/02
CPC分类号： H03F3/45475 , H03F2203/45048
摘要： Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.
摘要翻译：公开了用于在存在IC工艺制造变化的情况下补偿SoC参数的工艺传感器的方法和系统的某些方面。一种方法的方面可以包括确定与单个集成电路内的至少一个晶体管相关联的工艺变化量。可以通过利用与工艺相关的电流，带隙电流和与晶体管的当前温度相关联的电流来补偿确定的工艺变化量。过程相关电流，带隙电流和与晶体管的当前温度相关联的电流可以被组合以产生输出电流。可以基于产生的输出电流来确定可变电阻器两端产生的电压。

3. 发明授权

US08456226B2 Method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations 失效
标题翻译：用于在存在IC工艺制造变化的情况下补偿SoC参数的过程传感器的方法和系统
公开(公告)号：US08456226B2
公开(公告)日：2013-06-04
申请号：US13545580
申请日：2012-07-10
申请人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
发明人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
IPC分类号： G05F3/02
CPC分类号： H03F3/45475 , H03F2203/45048
摘要： Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.
摘要翻译：公开了用于在存在IC工艺制造变化的情况下补偿SoC参数的工艺传感器的方法和系统的某些方面。一种方法的方面可以包括确定与单个集成电路内的至少一个晶体管相关联的工艺变化量。可以通过利用与工艺相关的电流，带隙电流和与晶体管的当前温度相关联的电流来补偿确定的工艺变化量。过程相关电流，带隙电流和与晶体管的当前温度相关联的电流可以被组合以产生输出电流。可以基于产生的输出电流来确定可变电阻器两端产生的电压。

4. 发明申请

US20120274397A1 METHOD AND SYSTEM FOR A PROCESS SENSOR TO COMPENSATE SOC PARAMETERS IN THE PRESENCE OF IC PROCESS MANUFACTURING VARIATIONS 失效
标题翻译：用于在IC工艺制造变化中存在SOC过程传感器补偿SOC参数的方法和系统
公开(公告)号：US20120274397A1
公开(公告)日：2012-11-01
申请号：US13545580
申请日：2012-07-10
申请人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
发明人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
IPC分类号： G05F3/02
CPC分类号： H03F3/45475 , H03F2203/45048
摘要： Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.
摘要翻译：公开了用于在存在IC工艺制造变化的情况下补偿SoC参数的工艺传感器的方法和系统的某些方面。一种方法的方面可以包括确定与单个集成电路内的至少一个晶体管相关联的工艺变化量。可以通过利用与工艺相关的电流，带隙电流和与晶体管的当前温度相关联的电流来补偿确定的工艺变化量。过程相关电流，带隙电流和与晶体管的当前温度相关联的电流可以被组合以产生输出电流。可以基于产生的输出电流来确定可变电阻器两端产生的电压。

5. 发明授权

US09024355B2 Embedded planar source/drain stressors for a finFET including a plurality of fins 有权
标题翻译：用于包括多个翅片的finFET的嵌入式平面源极/漏极应力源
公开(公告)号：US09024355B2
公开(公告)日：2015-05-05
申请号：US13483200
申请日：2012-05-30
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/02 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66484 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7831 , H01L29/7848 , H01L29/785
摘要： Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.
摘要翻译：翅片限定掩模结构形成在具有第一半导体材料的半导体材料层上，并且在其上形成一次性栅极结构。在一次性栅极结构周围形成栅极间隔物，随后去除鳍状物限定掩模结构的物理暴露部分。使用一次性栅极结构和栅极间隔物作为蚀刻掩模来凹入半导体材料层以形成凹入的半导体材料部分。通过选择性沉积具有与第一半导体材料不同的晶格常数的第二半导体材料，在凹入的半导体材料部分上形成嵌入式平面源极/漏极应力。在形成平坦化介电层之后，去除一次性栅极结构。使用鳍状限定掩模结构作为蚀刻掩模形成多个半导体鳍。在多个半导体鳍片上形成替换栅极结构。

6. 发明授权

US08981478B2 Recessed source and drain regions for FinFETs 有权
标题翻译：嵌入式FinFET的源极和漏极区域
公开(公告)号：US08981478B2
公开(公告)日：2015-03-17
申请号：US13611335
申请日：2012-09-12
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.
摘要翻译：半导体器件和方法包括通过在半导体层上限定翅片硬掩模来形成鳍状场效应晶体管，在散热片硬掩模上形成虚拟结构，以在半导体层上建立平面区域，去除超出鳍片硬掩模的一部分蚀刻与虚拟结构相邻的半导体层，以产生凹陷的源极和漏极区域，去除虚设结构，蚀刻平面区域中的半导体层以产生鳍片，以及在鳍片上形成栅极叠层。

7. 发明授权

US08949080B2 Methods of designing integrated circuits and systems thereof 有权
标题翻译：设计集成电路的方法及其系统
公开(公告)号：US08949080B2
公开(公告)日：2015-02-03
申请号：US12862991
申请日：2010-08-25
申请人： Kuo-Tsai Li , Paul Chang , Andy Chang
发明人： Kuo-Tsai Li , Paul Chang , Andy Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5068 , G06F17/5081
摘要： A method of designing an integrated circuit includes performing a pre-layout simulation of the integrated circuit. The pre-layout simulation is performed using a netlist generated from a process design kit (PDK) file. The PDK file includes a plurality of device model cards that are assigned to plurality of devices. The plurality of devices include a first device having at least one parasitic diode that is associated with at least one isolation well, the PDK file including information of the at least one parasitic diode. A design layout of the integrated circuit corresponding to a result of the pre-layout simulation is generated.
摘要翻译：集成电路的设计方法包括执行集成电路的预布局仿真。使用从过程设计工具包（PDK）文件生成的网表执行预布局模拟。 PDK文件包括分配给多个设备的多个设备模型卡。多个器件包括具有至少一个与至少一个隔离阱相关联的寄生二极管的第一器件，该PDK文件包括至少一个寄生二极管的信息。生成对应于预布局仿真结果的集成电路的设计布局。

8. 发明申请

US20130320399A1 EMBEDDED PLANAR SOURCE/DRAIN STRESSORS FOR A FINFET INCLUDING A PLURALITY OF FINS 有权
标题翻译：嵌入式平面电源/漏极应力器，包括多个FINS
公开(公告)号：US20130320399A1
公开(公告)日：2013-12-05
申请号：US13483200
申请日：2012-05-30
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66484 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7831 , H01L29/7848 , H01L29/785
摘要： Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.
摘要翻译：翅片限定掩模结构形成在具有第一半导体材料的半导体材料层上，并且在其上形成一次性栅极结构。在一次性栅极结构周围形成栅极间隔物，随后去除鳍状物限定掩模结构的物理暴露部分。使用一次性栅极结构和栅极间隔物作为蚀刻掩模来凹入半导体材料层以形成凹入的半导体材料部分。通过选择性沉积具有与第一半导体材料不同的晶格常数的第二半导体材料，在凹入的半导体材料部分上形成嵌入式平面源极/漏极应力。在形成平坦化介电层之后，去除一次性栅极结构。使用鳍状限定掩模结构作为蚀刻掩模形成多个半导体鳍。在多个半导体鳍片上形成替换栅极结构。

9. 发明申请

US20130214357A1 NON-PLANAR MOSFET STRUCTURES WITH ASYMMETRIC RECESSED SOURCE DRAINS AND METHODS FOR MAKING THE SAME 有权
标题翻译：具有不对称吸收源排水的非平面MOSFET结构及其制造方法
公开(公告)号：US20130214357A1
公开(公告)日：2013-08-22
申请号：US13398339
申请日：2012-02-16
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/0657 , H01L29/66795
摘要： Non-planar Metal Oxide Field Effect Transistors (MOSFETs) and methods for making non-planar MOSFETs with asymmetric, recessed source and drains having improved extrinsic resistance and fringing capacitance. The methods include a fin-last, replacement gate process to form the non-planar MOSFETs and employ a retrograde metal lift-off process to form the asymmetric source/drain recesses. The lift-off process creates one recess which is off-set from a gate structure while a second recess is aligned with the structure. Thus, source/drain asymmetry is achieved by the physical structure of the source/drains, and not merely by ion implantation. The resulting non-planar device has a first channel of a fin contacting a substantially undoped area on the drain side and a doped area on the source side, thus the first channel is asymmetric. A channel on atop surface of a fin is symmetric because it contacts doped areas on both the drain and source sides.
摘要翻译：非平面金属氧化物场效应晶体管（MOSFET）和用于制造具有改进的外在电阻和边缘电容的具有不对称，凹陷源极和漏极的非平面MOSFET的方法。这些方法包括最后一个替代栅极工艺，以形成非平面MOSFET并且采用逆向金属剥离工艺来形成不对称的源极/漏极凹槽。剥离过程产生一个从门结构偏离的凹槽，而第二凹槽与结构对准。因此，源/漏不对称性通过源极/漏极的物理结构实现，而不仅仅是通过离子注入来实现。所得到的非平面器件具有接触漏极侧的基本上未掺杂的区域和源极侧的掺杂区域的翅片的第一通道，因此第一通道是不对称的。鳍的顶表面上的通道是对称的，因为它接触漏极和源极侧上的掺杂区域。

10. 发明授权

US08513099B2 Epitaxial source/drain contacts self-aligned to gates for deposited FET channels 有权
标题翻译：外延源极/漏极接触件自对准到用于沉积FET通道的栅极
公开(公告)号：US08513099B2
公开(公告)日：2013-08-20
申请号：US12817733
申请日：2010-06-17
申请人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L51/0545 , B82Y10/00 , H01L27/283 , H01L51/0012 , H01L51/0048 , H01L51/0525
摘要： A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
摘要翻译：提供了一种形成自对准器件的方法，包括将碳纳米管（CNT）沉积到晶体介质衬底上，隔离包含CNT位置的晶体介质衬底的一部分，在栅极电介质层和栅电极栅叠层 CNT同时保持其结构完整性，并且形成外延源极和漏极区域，其与从栅极介电层和栅电极栅极叠层暴露的晶体介质衬底上的CNT的部分接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式