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41. 发明授权

US07186664B2 Methods and structures for metal interconnections in integrated circuits 有权
标题翻译：集成电路中金属互连的方法和结构
公开(公告)号：US07186664B2
公开(公告)日：2007-03-06
申请号：US11104160
申请日：2005-04-12
申请人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
发明人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76877 , H01L21/7682 , H01L21/76886 , H01L23/53271 , H01L2221/1047 , H01L2924/0002 , Y10S438/933 , H01L2924/00
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.
摘要翻译：典型的集成电路制造需要用金属线互连数百万个微观晶体管和电阻器。使金属丝与底层绝缘体齐平或共面需要在绝缘层中挖沟，然后用金属填充沟槽以形成导线。本发明提供了一种制造共面金属线的新的“无沟槽”或“自平坦化”方法。具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使铝或铝合金与非氧化区域反应。该反应用铝代替或替代非氧化区域以形成与第一层共面的金属线。另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。

42. 发明授权

US06504224B1 Methods and structures for metal interconnections in integrated circuits 有权
标题翻译：集成电路中金属互连的方法和结构
公开(公告)号：US06504224B1
公开(公告)日：2003-01-07
申请号：US09651471
申请日：2000-08-30
申请人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
发明人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L2900
CPC分类号： H01L21/76877 , H01L21/7682 , H01L21/76886 , H01L23/53271 , H01L2221/1047 , H01L2924/0002 , Y10S438/933 , H01L2924/00
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. Trench digging is time consuming and costly. Accordingly, the invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces capacitance which, in turn, enables faster, more-efficient integrated circuits.
摘要翻译：典型的集成电路制造需要用金属线互连数百万个微观晶体管和电阻器。使金属丝与底层绝缘体齐平或共面需要在绝缘层中挖沟，然后用金属填充沟槽以形成导线。沟槽挖掘费时费力。因此，本发明提供了一种制造共面金属线的新的“无沟槽”或“自平坦化”方法。具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使铝或铝合金与非氧化区域反应。该反应用铝代替或替代非氧化区域以形成与第一层共面的金属线。另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。因此，本发明不仅消除了常规方法的耗时的沟槽挖掘步骤，而且降低了电容，进而实现了更快，更高效的集成电路。

43. 发明授权

US5920121A Methods and structures for gold interconnections in integrated circuits 失效
公开(公告)号：US5920121A
公开(公告)日：1999-07-06
申请号：US30188
申请日：1998-02-25
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53252 , H01L23/53242 , H01L2924/0002
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as gold. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar gold wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts gold with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with gold to form gold wires coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces resistance and capacitance which, in turn, enable faster, more-efficient integrated circuits.

44. 发明授权

US08679928B2 Methods for stressing transistor channels of a semiconductor device structure 有权
标题翻译：用于胁迫半导体器件结构的晶体管沟道的方法
公开(公告)号：US08679928B2
公开(公告)日：2014-03-25
申请号：US13611249
申请日：2012-09-12
申请人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L21/335
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/66492 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
摘要翻译：本发明包括用于应力半导体器件结构的晶体管沟道的方法。这样的方法包括形成邻近源极/漏极区域的所谓的近表面“纳米空腔”，形成与纳米空间相邻并包括纳米空间的源极/漏极区域的延伸部分，以及将扩大或收缩纳米孔隙的类型的植入物质分别取决于晶体管通道中在纳米腔之间是否需要压缩应变，如在PMOS场效应晶体管中的压应变或晶体管通道中的拉伸应变，如在NMOS场效应晶体管中，以增强载流子迁移率和晶体管速度。还公开了包括这些特征的半导体器件结构和半导体器件。

45. 发明授权

US07750379B2 Metal-substituted transistor gates 失效
标题翻译：金属取代晶体管栅极
公开(公告)号：US07750379B2
公开(公告)日：2010-07-06
申请号：US11445000
申请日：2006-06-01
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L29/772
CPC分类号： H01L21/02164 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/28079 , H01L21/28194 , H01L21/28229 , H01L21/3142 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L2924/0002 , Y10S438/926 , Y10T428/12354 , H01L2924/00
摘要： One aspect of this disclosure relates to an integrated circuit structure. An integrated circuit structure embodiment includes a substrate, a gate dielectric over the substrate, a carbon structure having a predetermined thickness in contact with and over the gate dielectric, and a layer of desired gate material for a transistor in contact with and over the carbon structure. The layer of desired gate material includes a predetermined thickness corresponding to the predetermined thickness of the carbon structure to support a metal substitution process to replace the carbon structure with the desired gate material. Other aspects and embodiments are provided herein.
摘要翻译：本公开的一个方面涉及集成电路结构。集成电路结构实施例包括衬底，衬底上的栅极电介质，具有与栅极电介质接触并且超过栅极电介质的预定厚度的碳结构，以及用于与碳结构接触并超过碳结构的晶体管的期望栅极材料层。所需栅极材料层包括对应于碳结构的预定厚度的预定厚度，以支持金属取代过程以用期望的栅极材料代替碳结构。本文提供了其它方面和实施例。

46. 发明授权

US07195999B2 Metal-substituted transistor gates 有权
公开(公告)号：US07195999B2
公开(公告)日：2007-03-27
申请号：US11176738
申请日：2005-07-07
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L21/336
CPC分类号： H01L21/02164 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/28079 , H01L21/28194 , H01L21/28229 , H01L21/3142 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L2924/0002 , Y10S438/926 , Y10T428/12354 , H01L2924/00
摘要： One aspect of this disclosure relates to a method for forming a transistor. According to various method embodiments, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor are formed. A desired gate material is substituted for the substitutable structure to provide the desired gate material on the gate dielectric. Some embodiments use carbon for the substitutable material, and some embodiments use silicon, germanium or silicon-germanium for the substitutable material. Some embodiments form a high-k gate dielectric, such as may be formed by an atomic layer deposition process, an evaporated deposition process, and a metal oxidation process. Other aspects and embodiments are provided herein.

47. 发明授权

US07190616B2 In-service reconfigurable DRAM and flash memory device 有权
标题翻译：在服务可重新配置的DRAM和闪存设备
公开(公告)号：US07190616B2
公开(公告)日：2007-03-13
申请号：US10894101
申请日：2004-07-19
申请人： Leonard Forbes , Paul A. Farrar
发明人： Leonard Forbes , Paul A. Farrar
IPC分类号： G11C11/34
CPC分类号： G11C14/00 , G11C11/404 , G11C11/405 , G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10823 , H01L27/10894 , H01L27/11526 , H01L27/11531 , H01L27/11534 , H01L27/11568
摘要： A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. One gate is a polysilicon gate and gate insulator that is adjacent to the floating body of the transistor and acts as a DRAM cell. The non-volatile memory cell is constructed on the other side of the pillar with a floating gate or NROM structure. The DRAM and non-volatile cells are linked by a drain region coupling the two cells to a memory array bitline. The bottom of trenches on either side of the pillar have source regions that are linked to respective source lines of the memory array.
摘要翻译：具有DRAM单元和非易失性存储单元的存储单元。非易失性存储单元可以包括闪存或NROM单元。存储单元包括具有双栅极的垂直浮体晶体管，一个在衬底的垂直柱的两侧。一个栅极是与晶体管的浮体相邻并用作DRAM单元的多晶硅栅极和栅极绝缘体。该非易失性存储单元构造在具有浮动栅极或NROM结构的柱体的另一侧上。 DRAM和非易失性单元通过将两个单元耦合到存储器阵列位线的漏极区域链接。柱的两侧的沟槽的底部具有与存储器阵列的各个源极线相连的源极区域。

48. 发明授权

US08293611B2 Implantation processes for straining transistor channels of semiconductor device structures and semiconductor devices with strained transistor channels 有权
标题翻译：具有应变晶体管沟道的半导体器件结构和半导体器件的应变晶体管沟道的植入过程
公开(公告)号：US08293611B2
公开(公告)日：2012-10-23
申请号：US11745814
申请日：2007-05-08
申请人： Arup Bhattacharyya , Leonard Forbes , Paul A Farrar
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A Farrar
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/66492 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
摘要翻译：本发明包括用于应力半导体器件结构的晶体管沟道的方法。这种方法包括形成邻近源极/漏极区域的所谓近表面纳米孔，形成邻近并包括纳米孔的源极/漏极区域的延伸部分，以及将扩大或收缩体积的类型的植入物质分别取决于在NMOS场效应晶体管中如在NMOS场效应晶体管中在纳米腔中的晶体管通道中是否需要压缩应变，如在PMOS场效应晶体管中的拉伸应变或拉伸应变，以增强载流子迁移率和晶体管速度。还公开了包括这些特征的半导体器件结构和半导体器件。

49. 发明授权

US07888744B2 Strained semiconductor, devices and systems and methods of formation 有权
标题翻译：应变半导体，器件和系统及其形成方法
公开(公告)号：US07888744B2
公开(公告)日：2011-02-15
申请号：US12346281
申请日：2008-12-30
申请人： Leonard Forbes , Paul A. Farrar
发明人： Leonard Forbes , Paul A. Farrar
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7846 , H01L21/26506 , H01L21/76232 , H01L29/6659 , H01L29/7833
摘要： In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein.
摘要翻译：在各种方法实施例中，器件区域被限定在半导体衬底中，并且隔离区域被限定为与器件区域相邻。器件区域具有通道区域，隔离区域具有体积。调整隔离区的体积以提供具有所需应变的通道区。在各种实施例中，调节隔离区域的体积包括将隔离区域从结晶区域转换为非晶区域以扩大隔离区域的体积并且为通道区域提供期望的压缩应变。在各种实施例中，调节隔离区域的体积包括将隔离区域从非晶区域转换为结晶区域以收缩隔离区域的体积，以提供具有期望拉伸应变的通道区域。本文提供了其它方面和实施例。

50. 发明授权

US07674698B2 Metal-substituted transistor gates 失效
标题翻译：金属取代晶体管栅极
公开(公告)号：US07674698B2
公开(公告)日：2010-03-09
申请号：US11444993
申请日：2006-06-01
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L21/336
CPC分类号： H01L21/02164 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/28079 , H01L21/28194 , H01L21/28229 , H01L21/3142 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L2924/0002 , Y10S438/926 , Y10T428/12354 , H01L2924/00
摘要： One aspect of this disclosure relates to a method for forming an integrated circuit. According to various embodiments of the method, a plurality of transistors is formed. For each transistor, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor are formed. At least two substitution processes are performed. Each substitution process includes substituting a desired gate material for the substitutable structure. Other aspects and embodiments are provided herein.
摘要翻译：本公开的一个方面涉及一种用于形成集成电路的方法。根据该方法的各种实施例，形成多个晶体管。对于每个晶体管，在衬底上形成栅极电介质，在栅极电介质上形成可取代的结构，并且形成用于晶体管的源/漏区。至少执行两个替换过程。每个取代过程包括用期望的栅极材料代替可替代结构。本文提供了其它方面和实施例。

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