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41. 发明申请

US20130207189A1 INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME 有权
标题翻译：具有降低硅氧烷接触电阻的上升源排水装置的集成电路及其制造方法
公开(公告)号：US20130207189A1
公开(公告)日：2013-08-15
申请号：US13852103
申请日：2013-03-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
IPC分类号： H01L29/78
CPC分类号： H01L29/66515 , H01L21/28518 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L23/485 , H01L27/0883 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
摘要翻译：结构具有至少一个场效应晶体管，其栅极堆叠设置在与栅极堆叠相邻的凸起的源极漏极结构之间。栅极堆叠和升高的源极漏极结构设置在半导体材料的表面上。该结构还包括覆盖栅极叠层和升高的源极漏极结构的场介电层，以及延伸穿过场电介质层的第一接触金属和第二接触金属。第一接触金属终止在通过第一凸起源极漏极结构的顶表面形成的第一沟槽中，并且第二接触金属终止于通过第二凸起源极漏极结构的顶表面形成的第二沟槽中。每个沟槽具有形成在沟槽的至少一部分的侧壁和底表面上的硅化物。还公开了制造该结构的方法。

42. 发明授权

US08507989B2 Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance 有权
标题翻译：极薄的绝缘体上半导体（ETSOI）FET，具有背栅极和降低的寄生电容
公开(公告)号：US08507989B2
公开(公告)日：2013-08-13
申请号：US13108282
申请日：2011-05-16
申请人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris
发明人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66
CPC分类号： H01L27/1203 , H01L21/764 , H01L21/84 , H01L29/42384 , H01L29/4908 , H01L29/78648 , H01L2029/42388
摘要： An extremely thin SOI MOSFET device on an SOI substrate is provided with a back gate layer on a Si substrate superimposed by a thin BOX layer; an extremely thin SOI layer (ETSOI) on top of the thin BOX layer; and an FET device on the ETSOI layer having a gate stack insulated by spacers. The thin BOX is formed under the ETSOI channel, and is provided with a thicker dielectric under source and drain to reduce the source/drain to back gate parasitic capacitance. The thicker dielectric portion is self-aligned with the gate. A void within the thicker dielectric portion is formed under the source/drain region. The back gate is determined by a region of semiconductor damaged by implantation, and the formation of an insulating layer by lateral etch and back filling with dielectric.
摘要翻译：在SOI衬底上的非常薄的SOI MOSFET器件在Si衬底上设置有由薄BOX层叠加的背栅层; 在薄BOX层顶部的非常薄的SOI层（ETSOI）; 并且在ETSOI层上的FET器件具有由间隔物绝缘的栅极堆叠。薄BOX形成在ETSOI通道下面，并在源极和漏极之间提供较厚的电介质，以减少源极/漏极到背栅极寄生电容。较厚的电介质部分与栅极自对准。较厚电介质部分内的空隙形成在源/漏区下。背栅由通过注入损坏的半导体区域确定，并且通过横向蚀刻形成绝缘层并且用电介质反向填充。

43. 发明授权

US08420464B2 Spacer as hard mask scheme for in-situ doping in CMOS finFETs 失效
标题翻译：隔膜作为CMOS finFET中原位掺杂的硬掩模方案
公开(公告)号：US08420464B2
公开(公告)日：2013-04-16
申请号：US13100589
申请日：2011-05-04
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
IPC分类号： H01L21/8238
CPC分类号： H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.
摘要翻译：一种制造半导体器件的方法，其包括至少两个翅片结构，其中所述至少两个翅片结构中的一个包括外延形成的原位掺杂的第二源极和漏极区域，其具有存在于鳍的侧壁上的刻面外侧壁结构体。在另一个实施例中，本发明还提供一种制造finFET的方法，其包括在鳍结构的侧壁中形成凹槽，并且在形成在鳍结构中的凹槽中外延形成延伸掺杂区域。还描述了通过上述方法形成的结构。

44. 发明申请

US20130071979A1 Field Effect Transistor Device with Raised Active Regions 失效
标题翻译：具有有源区域的场效应晶体管器件
公开(公告)号：US20130071979A1
公开(公告)日：2013-03-21
申请号：US13606382
申请日：2012-09-07
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/336
CPC分类号： H01L29/41783 , H01L29/165 , H01L29/41775 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.
摘要翻译：一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面，第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。

45. 发明授权

US08343877B2 Angle ion implant to re-shape sidewall image transfer patterns 有权
标题翻译：角度离子注入重新形成侧壁图像传输模式
公开(公告)号：US08343877B2
公开(公告)日：2013-01-01
申请号：US12614952
申请日：2009-11-09
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/28132 , H01L21/26586 , H01L29/66787
摘要： A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features.
摘要翻译：一种用于制造集成电路的特征的方法及其装置包括在半导体器件的表面上形成第一结构并在第一结构的周围形成间隔物。将角度离子注入施加到器件，使得间隔物具有来自成角度离子注入的保护部分和未受保护部分，其中未保护部分具有大于被保护部分的蚀刻速率的蚀刻速率。相对于受保护部分，非保护部分和第一结构被选择性地去除。将间隔物的受保护部分下面的层图案化以形成集成电路特征。

46. 发明申请

US20120322251A1 Borderless Contacts For Semiconductor Devices 有权
标题翻译：半导体器件无边界接触
公开(公告)号：US20120322251A1
公开(公告)日：2012-12-20
申请号：US13597331
申请日：2012-08-29
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L21/28
CPC分类号： H01L29/42364 , H01L21/76831 , H01L21/76897 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material.
摘要翻译：在本发明的一个示例性实施例中，一种方法（例如，制造具有无边界接触的半导体器件）包括：在衬底上形成第一栅极结构; 在所述第一栅极结构上沉积层间电介质; 平面化所述层间电介质以暴露所述第一栅极结构的顶表面; 去除所述第一栅极结构的至少一部分; 形成第二栅极结构来代替第一栅极结构; 通过去除所述层间电介质的一部分来形成所述无边界接触的接触区域; 以及通过用含金属材料填充接触区域来形成无边界接触。

47. 发明授权

US08324036B2 Device having and method for forming fins with multiple widths for an integrated circuit 有权
标题翻译：具有用于形成用于集成电路的多个宽度的散热片的装置和方法
公开(公告)号：US08324036B2
公开(公告)日：2012-12-04
申请号：US12614986
申请日：2009-11-09
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L21/84
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
摘要翻译：一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

48. 发明授权

US08318574B2 SOI trench DRAM structure with backside strap 有权
标题翻译：具有背面带的SOI沟槽DRAM结构
公开(公告)号：US08318574B2
公开(公告)日：2012-11-27
申请号：US12847208
申请日：2010-07-30
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.
摘要翻译：在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。

49. 发明申请

US20120286350A1 TUNNEL FIELD EFFECT TRANSISTOR 失效
标题翻译：隧道场效应晶体管
公开(公告)号：US20120286350A1
公开(公告)日：2012-11-15
申请号：US13558518
申请日：2012-07-26
申请人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side.
摘要翻译：公开了一种以不对称隧道FET（TFET）为特征的FET器件。 TFET包括栅极堆叠，栅极堆叠下方的沟道区域，邻接栅极叠层的第一和第二结，并且能够与沟道电连接。第一接头和第二接头具有不同的导电类型。 TFET还包括间隔物结构，使得栅极叠层的一侧上的间隔物形成比另一侧更薄。

50. 发明授权

US08309447B2 Method for integrating multiple threshold voltage devices for CMOS 有权
标题翻译：用于集成多个CMOS阈值电压器件的方法
公开(公告)号：US08309447B2
公开(公告)日：2012-11-13
申请号：US12855273
申请日：2010-08-12
申请人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
发明人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823481 , H01L21/823878
摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.
摘要翻译：公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。因此，本公开的方法避免了短信道惩罚。此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。

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