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1. 发明授权

US08324036B2 Device having and method for forming fins with multiple widths for an integrated circuit 有权
标题翻译：具有用于形成用于集成电路的多个宽度的散热片的装置和方法
公开(公告)号：US08324036B2
公开(公告)日：2012-12-04
申请号：US12614986
申请日：2009-11-09
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L21/84
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
摘要翻译：一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

2. 发明授权

US08569868B2 Device having and method for forming fins with multiple widths 有权
标题翻译：具有用于形成多个宽度的翅片的装置和方法
公开(公告)号：US08569868B2
公开(公告)日：2013-10-29
申请号：US13552296
申请日：2012-07-18
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.
摘要翻译：公开了一种用于半导体器件的结构。该结构包括第一特征和第二特征。第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

3. 发明申请

US20120280365A1 DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS 有权
标题翻译：具有形成具有多个宽度的FINS的装置和方法
公开(公告)号：US20120280365A1
公开(公告)日：2012-11-08
申请号：US13552296
申请日：2012-07-18
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.
摘要翻译：公开了一种用于半导体器件的结构。该结构包括第一特征和第二特征。第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

4. 发明申请

US20110108961A1 DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS 有权
标题翻译：具有形成具有多个宽度的FINS的装置和方法
公开(公告)号：US20110108961A1
公开(公告)日：2011-05-12
申请号：US12614986
申请日：2009-11-09
申请人： KANGGUO CHENG , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： KANGGUO CHENG , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06 , H01L21/302
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
摘要翻译：一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

5. 发明申请

US20110291188A1 STRAINED FINFET 审中-公开
标题翻译：应变FINFET
公开(公告)号：US20110291188A1
公开(公告)日：2011-12-01
申请号：US12787383
申请日：2010-05-25
申请人： Kangguo Cheng , Bruce B. Doris , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7853
摘要： A FinFET is described incorporating at least two fins extending from a common Si containing layer and epitaxial material grown from the common layer and from sidewalls of the fins to introduce strain to the common layer and the fins to increase carrier mobility.
摘要翻译：描述了FinFET，其包括从共同的含Si层延伸的至少两个翅片和从公共层和翅片的侧壁生长的外延材料，以将应变引入公共层和翅片以增加载流子迁移率。

6. 发明授权

US09041116B2 Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs) 有权
公开(公告)号：US09041116B2
公开(公告)日：2015-05-26
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/092 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

7. 发明申请

US20140024191A1 METHOD OF MULTIPLE PATTERNING TO FORM SEMICONDUCTOR DEVICES 有权
标题翻译：多种图案形成半导体器件的方法
公开(公告)号：US20140024191A1
公开(公告)日：2014-01-23
申请号：US13555240
申请日：2012-07-23
申请人： Kuang-Jung Chen , Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Sen Liu
发明人： Kuang-Jung Chen , Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Sen Liu
IPC分类号： H01L21/31 , H01L21/336
CPC分类号： H01L21/0274 , H01L21/26586 , H01L21/3081 , H01L21/76229 , H01L21/76283 , H01L29/517 , H01L29/66575 , H01L29/78
摘要： A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.
摘要翻译：使用单个掩模和混合光致抗蚀剂形成半导体器件的不同结构的方法。该方法包括：在半导体衬底上施加第一光致抗蚀剂层; 使用光掩模图案化第一光致抗蚀剂层以形成第一图案化光致抗蚀剂层; 使用所述第一图案化的光致抗蚀剂层形成半导体器件的第一结构; 去除第一图案化光致抗蚀剂层; 在所述半导体衬底上施加第二光致抗蚀剂层; 使用光掩模图案化第二光致抗蚀剂层以形成第二图案化光致抗蚀剂层; 使用所述第二图案化的光致抗蚀剂层形成半导体器件的第二结构; 去除第二图案化光致抗蚀剂层; 并且其中所述第一或第二光致抗蚀剂层是包含混合光致抗蚀剂的混合光致抗蚀剂层。

8. 发明授权

US08871596B2 Method of multiple patterning to form semiconductor devices 有权
标题翻译：多重图形化形成半导体器件的方法
公开(公告)号：US08871596B2
公开(公告)日：2014-10-28
申请号：US13555240
申请日：2012-07-23
申请人： Kuang-Jung Chen , Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Sen Liu
发明人： Kuang-Jung Chen , Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Sen Liu
IPC分类号： H01L21/31
CPC分类号： H01L21/0274 , H01L21/26586 , H01L21/3081 , H01L21/76229 , H01L21/76283 , H01L29/517 , H01L29/66575 , H01L29/78
摘要： A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.
摘要翻译：使用单个掩模和混合光致抗蚀剂形成半导体器件的不同结构的方法。该方法包括：在半导体衬底上施加第一光致抗蚀剂层; 使用光掩模图案化第一光致抗蚀剂层以形成第一图案化光致抗蚀剂层; 使用所述第一图案化的光致抗蚀剂层形成半导体器件的第一结构; 去除第一图案化光致抗蚀剂层; 在所述半导体衬底上施加第二光致抗蚀剂层; 使用光掩模图案化第二光致抗蚀剂层以形成第二图案化光致抗蚀剂层; 使用所述第二图案化的光致抗蚀剂层形成半导体器件的第二结构; 去除第二图案化光致抗蚀剂层; 并且其中所述第一或第二光致抗蚀剂层是包含混合光致抗蚀剂的混合光致抗蚀剂层。

9. 发明申请

US20130313643A1 Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) 有权
标题翻译：用于调制高K金属栅场效应晶体管（FET）的阈值电压的结构和方法
公开(公告)号：US20130313643A1
公开(公告)日：2013-11-28
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/12 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
摘要翻译：一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离存在于第二导电装置区域上的高k栅介质层。连接栅极导体形成在高k栅介质层的第一部分和第二部分上。连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。用含氧气氛曝光改变暴露的半导体器件的阈值电压。

10. 发明授权

US08889562B2 Double patterning method 有权
标题翻译：双重图案化方法
公开(公告)号：US08889562B2
公开(公告)日：2014-11-18
申请号：US13555306
申请日：2012-07-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01B13/00 , H01B19/04 , H01L21/0337 , H01L21/3081 , H01L21/32134 , H01L21/32137
摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
摘要翻译：公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

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