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41. 发明授权

US08598605B2 Semiconductor light-emitting device 有权
标题翻译：半导体发光装置
公开(公告)号：US08598605B2
公开(公告)日：2013-12-03
申请号：US13601454
申请日：2012-08-31
申请人： Naoharu Sugiyama , Taisuke Sato , Kotaro Zaima , Jumpei Tajima , Toshiki Hikosaka , Yoshiyuki Harada , Hisashi Yoshida , Shinya Nunoue
发明人： Naoharu Sugiyama , Taisuke Sato , Kotaro Zaima , Jumpei Tajima , Toshiki Hikosaka , Yoshiyuki Harada , Hisashi Yoshida , Shinya Nunoue
IPC分类号： H01L33/00 , H01L21/00
CPC分类号： H01L33/32 , H01L33/06 , H01L33/12
摘要： According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.
摘要翻译：根据一个实施例，半导体发光器件包括：包含氮化物半导体晶体并且在（0001）表面中具有拉伸应力的第一导电类型的第一半导体层; 含有氮化物半导体晶体并在（0001）表面具有拉伸应力的第二导电类型的第二半导体层; 设置在所述第一半导体层和所述第二半导体层之间的包含氮化物半导体晶体并且具有大于所述第一半导体层的晶格常数的平均晶格常数的发光层; 以及第一应力施加层，其设置在与所述第一半导体层的所述发光层相对的一侧上，并向所述第一半导体层施加压缩应力。

42. 发明申请

US20130234178A1 SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体发光器件及其制造方法
公开(公告)号：US20130234178A1
公开(公告)日：2013-09-12
申请号：US13601015
申请日：2012-08-31
申请人： Satoshi Mitsugi , Naoharu Sugiyama , Taisuke Sato , Shinya Nunoue
发明人： Satoshi Mitsugi , Naoharu Sugiyama , Taisuke Sato , Shinya Nunoue
IPC分类号： H01L33/60
CPC分类号： H01L33/60 , H01L33/0079 , H01L33/12 , H01L33/20
摘要： According to one embodiment, a semiconductor light emitting device includes a silicon substrate, a buffer layer, a foundation semiconductor layer, a first semiconductor layer, a light emitting unit and a second semiconductor layer. The buffer layer is provided on a part of a major surface of the silicon substrate. The foundation semiconductor layer is crystal-grown from an upper surface of the buffer layer, covers a non-formed region of the major surface where the buffer layer is not provided, and is spaced apart from the non-formed region. The first semiconductor layer is provided on the foundation semiconductor layer and has a first conductivity type. The light emitting unit is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting unit and has a second conductivity type.
摘要翻译：根据一个实施例，半导体发光器件包括硅衬底，缓冲层，基底半导体层，第一半导体层，发光单元和第二半导体层。缓冲层设置在硅衬底的主表面的一部分上。基底半导体层从缓冲层的上表面晶体生长，覆盖没有设置缓冲层的主表面的非形成区域，并与非形成区域间隔开。第一半导体层设置在基底半导体层上并且具有第一导电类型。发光单元设置在第一半导体层上。第二半导体层设置在发光单元上并具有第二导电类型。

43. 发明申请

US20130234106A1 SEMICONDUCTOR LIGHT-EMITTING DEVICE 有权
标题翻译：半导体发光器件
公开(公告)号：US20130234106A1
公开(公告)日：2013-09-12
申请号：US13601454
申请日：2012-08-31
申请人： Naoharu Sugiyama , Taisuke Sato , Kotaro Zaima , Jumpei Tajima , Toshiki Hikosaka , Yoshiyuki Harada , Hisashi Yoshida , Shinya Nunoue
发明人： Naoharu Sugiyama , Taisuke Sato , Kotaro Zaima , Jumpei Tajima , Toshiki Hikosaka , Yoshiyuki Harada , Hisashi Yoshida , Shinya Nunoue
IPC分类号： H01L33/12
CPC分类号： H01L33/32 , H01L33/06 , H01L33/12
摘要： According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.
摘要翻译：根据一个实施例，半导体发光器件包括：包含氮化物半导体晶体并且在（0001）表面中具有拉伸应力的第一导电类型的第一半导体层; 含有氮化物半导体晶体并在（0001）表面具有拉伸应力的第二导电类型的第二半导体层; 设置在所述第一半导体层和所述第二半导体层之间的包含氮化物半导体晶体并且具有大于所述第一半导体层的晶格常数的平均晶格常数的发光层; 以及第一应力施加层，其设置在与所述第一半导体层的所述发光层相对的一侧上，并向所述第一半导体层施加压缩应力。

44. 发明申请

US20060281234A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060281234A1
公开(公告)日：2006-12-14
申请号：US11449687
申请日：2006-06-09
申请人： Naoharu Sugiyama , Norio Hirashita , Tsutomu Tezuka
发明人： Naoharu Sugiyama , Norio Hirashita , Tsutomu Tezuka
IPC分类号： H01L21/84
CPC分类号： H01L29/78687 , H01L29/045
摘要： A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to form a protective oxide film on a surface of the SiGe layer. Next, the substrate having the protective oxide film is heated in a non-oxidizing atmosphere to a second temperature higher than the first temperature. Further, heat treatment is performed on the substrate thus heated, in an oxidizing atmosphere at a temperature equal to or higher than the second temperature, to form oxide the SiGe layer, make the SiGe layer thinner and increasing Ge concentration in the SiGe layer, thus forming a SiGe layer having the increased Ge concentration.
摘要翻译：一种制造半导体器件的方法。在该方法中，制备了包括掩埋氧化物膜和形成在掩埋氧化膜上的SiGe层的衬底。然后，在等于或低于第一温度的温度下在基板上进行热处理，以在SiGe层的表面上形成保护氧化膜。接着，将具有保护氧化膜的基板在非氧化性气氛中加热至高于第一温度的第二温度。此外，在等于或高于第二温度的氧化气氛中对如此加热的基板进行热处理，以氧化SiGe层，使SiGe层更薄并增加SiGe层中的Ge浓度，从而形成具有增加的Ge浓度的SiGe层。

45. 发明授权

US06369438B1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06369438B1
公开(公告)日：2002-04-09
申请号：US09468923
申请日：1999-12-22
申请人： Naoharu Sugiyama , Atsushi Kurobe
发明人： Naoharu Sugiyama , Atsushi Kurobe
IPC分类号： H01L31117
CPC分类号： H01L21/7624 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L29/1054 , H01L29/157 , H01L29/7842 , H01L31/028
摘要： A method of manufacturing a semiconductor device comprising the steps of forming a first crystal silicon layer doped with oxygen on a single crystal silicon substrate, forming a crystal silicon-germanium layer on the first crystal silicon layer, forming a second crystal silicon layer on the crystal silicon-germanium layer, and imparting strain to the second crystal silicon layer by a thermal treatment.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在单晶硅衬底上形成掺杂有氧的第一晶体硅层，在第一晶体硅层上形成晶体硅 - 锗层，在晶体上形成第二晶体硅层硅锗层，并通过热处理赋予第二晶体硅层的应变。

46. 发明授权

US6060743A Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same 失效
标题翻译：具有多层IV族纳米晶体量子点浮栅的半导体存储器件及其制造方法
公开(公告)号：US6060743A
公开(公告)日：2000-05-09
申请号：US82613
申请日：1998-05-20
申请人： Naoharu Sugiyama , Tsutomu Tezuka , Riichi Katoh , Atsushi Kurobe , Tetsufumi Tanamoto
发明人： Naoharu Sugiyama , Tsutomu Tezuka , Riichi Katoh , Atsushi Kurobe , Tetsufumi Tanamoto
IPC分类号： H01L29/788 , H01L21/336 , H01L29/06 , H01L29/15
CPC分类号： B82Y10/00 , H01L29/7883 , H01L29/7888 , Y10S438/962
摘要： The semiconductor device comprises a first insulating layer formed on the semiconductor substrate, at least one double-deck semiconductor nanocrystal formed on the first insulating layer, the at least one double-deck semiconductor nanocrystal comprising a first semiconductor nanocrystal and a second semiconductor nanocrystal stacked one upon the other via a second insulating layer, and a third insulating layer selectively formed on the first insulating layer so as to cover the at least one double-deck semiconductor nanocrystal.
摘要翻译：所述半导体器件包括形成在所述半导体衬底上的第一绝缘层，形成在所述第一绝缘层上的至少一个双层半导体纳米晶体，所述至少一个双层半导体纳米晶体包括第一半导体纳米晶体和第二半导体纳米晶体，另一方面通过第二绝缘层，以及选择性地形成在第一绝缘层上以覆盖至少一个双层半导体纳米晶体的第三绝缘层。

47. 发明授权

US08174095B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08174095B2
公开(公告)日：2012-05-08
申请号：US13037049
申请日：2011-02-28
申请人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译：半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在通道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。

48. 发明授权

US07759228B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07759228B2
公开(公告)日：2010-07-20
申请号：US11449687
申请日：2006-06-09
申请人： Naoharu Sugiyama , Norio Hirashita , Tsutomu Tezuka
发明人： Naoharu Sugiyama , Norio Hirashita , Tsutomu Tezuka
IPC分类号： H01L21/84 , H01L21/324 , H01L21/20
CPC分类号： H01L29/78687 , H01L29/045
摘要： A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to form a protective oxide film on a surface of the SiGe layer. Next, the substrate having the protective oxide film is heated in a non-oxidizing atmosphere to a second temperature higher than the first temperature. Further, heat treatment is performed on the substrate thus heated, in an oxidizing atmosphere at a temperature equal to or higher than the second temperature, to form oxide the SiGe layer, make the SiGe layer thinner and increasing Ge concentration in the SiGe layer, thus forming a SiGe layer having the increased Ge concentration.
摘要翻译：一种制造半导体器件的方法。在该方法中，制备了包括掩埋氧化物膜和形成在掩埋氧化膜上的SiGe层的衬底。然后，在等于或低于第一温度的温度下在基板上进行热处理，以在SiGe层的表面上形成保护氧化膜。接着，将具有保护氧化膜的基板在非氧化性气氛中加热至高于第一温度的第二温度。此外，在等于或高于第二温度的氧化气氛中对如此加热的基板进行热处理，以氧化SiGe层，使SiGe层更薄并增加SiGe层中的Ge浓度，从而形成具有增加的Ge浓度的SiGe层。

49. 发明授权

US07619239B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07619239B2
公开(公告)日：2009-11-17
申请号：US11437730
申请日：2006-05-22
申请人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
发明人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.
摘要翻译：半导体器件包括形成在绝缘层上的半导体层上的n沟道MIS晶体管和p沟道MIS晶体管，其中n沟道MIS晶体管的沟道由具有双轴拉伸应变的应变Si层形成， p沟道MIS晶体管的沟道由在沟道长度方向上具有单轴压缩应变的应变SiGe层形成。

50. 发明申请

US20060266996A1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US20060266996A1
公开(公告)日：2006-11-30
申请号：US11437730
申请日：2006-05-22
申请人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
发明人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
IPC分类号： H01L31/00
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

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