专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07619239B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07619239B2
公开(公告)日：2009-11-17
申请号：US11437730
申请日：2006-05-22
申请人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
发明人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.
摘要翻译：半导体器件包括形成在绝缘层上的半导体层上的n沟道MIS晶体管和p沟道MIS晶体管，其中n沟道MIS晶体管的沟道由具有双轴拉伸应变的应变Si层形成， p沟道MIS晶体管的沟道由在沟道长度方向上具有单轴压缩应变的应变SiGe层形成。

2. 发明申请

US20060266996A1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US20060266996A1
公开(公告)日：2006-11-30
申请号：US11437730
申请日：2006-05-22
申请人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
发明人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
IPC分类号： H01L31/00
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

3. 发明授权

US07622773B2 Semiconductor device including multi-gate metal-insulator-semiconductor (MIS) transistor 有权
标题翻译：包括多栅极金属 - 绝缘体 - 半导体（MIS）晶体管的半导体器件
公开(公告)号：US07622773B2
公开(公告)日：2009-11-24
申请号：US11705450
申请日：2007-02-13
申请人： Toshifumi Irisawa , Toshinori Numata , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Toshinori Numata , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L27/12
CPC分类号： H01L29/7853 , H01L29/66636 , H01L29/66795 , H01L29/78687
摘要： In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.
摘要翻译：在包括在多个表面上具有沟道的多栅极MIS晶体管的半导体器件中，在绝缘膜上沿着给定方向形成的岛状半导体层的侧表面上的栅极绝缘膜上形成栅电极，并且源极/漏极形成为与半导体层接触。半导体层具有沿给定方向的多个侧表面。由相邻侧面形成的所有角度大于90°。垂直于给定方向的部分垂直和水平对称。

4. 发明申请

US20070241399A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070241399A1
公开(公告)日：2007-10-18
申请号：US11705450
申请日：2007-02-13
申请人： Toshifumi Irisawa , Toshinori Numata , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Toshinori Numata , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7853 , H01L29/66636 , H01L29/66795 , H01L29/78687
摘要： In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.
摘要翻译：在包括在多个表面上具有沟道的多栅极MIS晶体管的半导体器件中，在绝缘膜上沿着给定方向形成的岛状半导体层的侧表面上的栅极绝缘膜上形成栅电极，并且源极/漏极形成为与半导体层接触。半导体层具有沿给定方向的多个侧表面。由相邻侧面形成的所有角度大于90°。垂直于给定方向的部分垂直和水平对称。

5. 发明申请

US20120241722A1 FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管
公开(公告)号：US20120241722A1
公开(公告)日：2012-09-27
申请号：US13240246
申请日：2011-09-22
申请人： Keiji Ikeda , Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka
发明人： Keiji Ikeda , Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka
IPC分类号： H01L29/165
CPC分类号： H01L29/4983 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/6656
摘要： A field effect transistor according to an embodiment includes: a semiconductor layer; a source region and a drain region formed at a distance from each other in the semiconductor layer; a gate insulating film formed on a portion of the semiconductor layer, the portion being located between the source region and the drain region; a gate electrode formed on the gate insulating film; and a gate sidewall formed on at least one of side faces of the gate electrode, the side faces being located on a side of the source region and on a side of the drain region, the gate sidewall being made of a high dielectric material. The source region and the drain region are separately-placed from the corresponding side faces of the gate electrode.
摘要翻译：根据实施例的场效应晶体管包括：半导体层; 在半导体层中形成为彼此相距一定距离的源极区域和漏极区域; 形成在半导体层的一部分上的栅极绝缘膜，该部分位于源极区域和漏极区域之间; 形成在栅极绝缘膜上的栅电极; 以及栅极侧壁，其形成在所述栅电极的至少一个侧面上，所述侧面位于所述源极区域的一侧，并且在所述漏极区域的侧面上，所述栅极侧壁由高介电材料制成。源极区域和漏极区域与栅电极的相应侧面分开设置。

6. 发明授权

US08008751B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08008751B2
公开(公告)日：2011-08-30
申请号：US11950716
申请日：2007-12-05
申请人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译：半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在通道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。

7. 发明申请

US20110147805A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147805A1
公开(公告)日：2011-06-23
申请号：US13037049
申请日：2011-02-28
申请人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译：半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在沟道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。

8. 发明申请

US20080135886A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080135886A1
公开(公告)日：2008-06-12
申请号：US11950716
申请日：2007-12-05
申请人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L29/04 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译：半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在通道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。

9. 发明授权

US08174095B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08174095B2
公开(公告)日：2012-05-08
申请号：US13037049
申请日：2011-02-28
申请人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译：半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在通道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。

10. 发明申请

US20060170011A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060170011A1
公开(公告)日：2006-08-03
申请号：US11235168
申请日：2005-09-27
申请人： Toshifumi Irisawa , Toshinori Numata
发明人： Toshifumi Irisawa , Toshinori Numata
IPC分类号： H01L29/768
CPC分类号： H01L29/0649 , H01L29/42392 , H01L29/7849 , H01L29/78687
摘要： A semiconductor device includes a gate-all-around MOSFET structure comprises a first semiconductor layer which is formed on a support substrate and which has a recess formed on a surface thereof, a second semiconductor layer formed on the first semiconductor layer and which has a part thereof formed to cross over the recess of the first semiconductor layer, a gate electrode which is formed through a gate insulation film to surround the crossing portion of the second semiconductor layer and which has parts other than the part located under the second semiconductor layer processed in a gate pattern, source and drain areas formed on the second semiconductor layer, and a sidewall insulation film which is formed on sidewall surfaces of the recess of the first semiconductor layer and which has a greater thickness than the gate insulation film.
摘要翻译：半导体器件包括栅极全环MOSFET结构，其包括形成在支撑衬底上并具有形成在其表面上的凹部的第一半导体层，形成在第一半导体层上的第二半导体层，其形成为跨越所述第一半导体层的凹部，栅电极，其通过栅极绝缘膜形成以围绕所述第二半导体层的交叉部分，并且具有除了位于所述第二半导体层下方的部分以外的部分形成在第二半导体层上的栅极图案，源极和漏极区域以及形成在第一半导体层的凹部的侧壁表面上并且具有比栅极绝缘膜更大的厚度的侧壁绝缘膜。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式