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41. 发明授权

US06555425B2 Method for manufacturing transistor 有权
公开(公告)号：US06555425B2
公开(公告)日：2003-04-29
申请号：US09880519
申请日：2001-06-12
申请人： Kuo-Tai Huang , Ellen Cheng
发明人： Kuo-Tai Huang , Ellen Cheng
IPC分类号： H01L218238
CPC分类号： H01L29/66583 , H01L21/28114 , H01L29/41783 , H01L29/42376 , H01L29/6656 , H01L29/7834
摘要： A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the polysilicon layer and the gate oxide layer and a source/drain formed in the substrate. A conformal dielectric layer is formed over the polysilicon layer, the offset spacer and the source/drain. A spacer is formed on the sidewall of a portion of the conformal dielectric layer over the offset spacer. A portion of the conformal dielectric layer is removed to expose the polysilicon layer and the source/drain. A selective epitaxial growth process is performed to form an epitaxial layer on the polysilicon layer and the source/drain. A portion of the epitaxial layer on the polysilicon layer, the polysilicon layer and the gate oxide layer together form a T-type gate structure.

42. 发明授权

US08736016B2 Strained isolation regions 有权
标题翻译：应变隔离区
公开(公告)号：US08736016B2
公开(公告)日：2014-05-27
申请号：US11759791
申请日：2007-06-07
申请人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
发明人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/7833 , H01L29/7843 , H01L29/7846
摘要： An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
摘要翻译：提供了具有局部应力源的隔离沟槽。根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。然后将电介质材料凹入到衬底的表面下方。在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。应力膜也可以在晶体管或其它半导体结构上延伸。

43. 发明授权

US08324090B2 Method to improve dielectric quality in high-k metal gate technology 有权
标题翻译：提高高k金属栅极技术介质质量的方法
公开(公告)号：US08324090B2
公开(公告)日：2012-12-04
申请号：US12338787
申请日：2008-12-18
申请人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Yong-Tian Hou , Carlos H. Diaz
发明人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Yong-Tian Hou , Carlos H. Diaz
IPC分类号： H01L21/4763 , H01L25/11 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和金属层。

44. 发明申请

US20120164822A1 METHODS OF FABRICATING HIGH-K METAL GATE DEVICES 有权
标题翻译：制造高K金属栅极器件的方法
公开(公告)号：US20120164822A1
公开(公告)日：2012-06-28
申请号：US13408016
申请日：2012-02-29
申请人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin
发明人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin
IPC分类号： H01L21/28
CPC分类号： H01L21/823828 , H01L21/3221 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
摘要翻译：公开了制造具有高k /金属栅极特征的半导体器件的方法。在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

45. 发明申请

US20100044800A1 High-K dielectric metal gate device structure 有权
标题翻译：高K电介质金属栅极器件结构
公开(公告)号：US20100044800A1
公开(公告)日：2010-02-25
申请号：US12589421
申请日：2009-10-23
申请人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
发明人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric.
摘要翻译：金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。

46. 发明申请

US20100041223A1 METHOD OF INTEGRATING HIGH-K/METAL GATE IN CMOS PROCESS FLOW 有权
标题翻译：在CMOS工艺流程中集成高K /金属栅的方法
公开(公告)号：US20100041223A1
公开(公告)日：2010-02-18
申请号：US12478509
申请日：2009-06-04
申请人： Ryan Chia-Jen Chen , Yih-Ann Lin , Jr Jung Lin , Yi-Shien Mor , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen
发明人： Ryan Chia-Jen Chen , Yih-Ann Lin , Jr Jung Lin , Yi-Shien Mor , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen
IPC分类号： H01L21/28
CPC分类号： H01L21/82385 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L29/0653 , H01L29/401 , H01L29/42372 , H01L29/4966 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer over the high-k dielectric layer, the first metal layer having a first work function, removing a portion of the first metal layer in the second active region, thereafter, forming a semiconductor layer over the first metal layer in the first active region and over the partially removed first metal layer in the second active region, forming a first gate stack in the first active region and a second gate stack in the second active region, removing the semiconductor layer from the first gate stack and from the second gate stack, and forming a second metal layer on the first metal layer in the first gate stack and on the partially removed first metal layer in the second gate stack, the second metal layer having a second work function.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成第一金属层，第一金属层具有第一在第二有源区中除去第一金属层的一部分，然后在第一有源区中的第一金属层上方和在第二有源区中的部分去除的第一金属层上方形成半导体层，形成第一在第一有源区中的栅极堆叠和第二有源区中的第二栅极堆叠，从第一栅极堆叠和第二栅极堆叠中去除半导体层，以及在第一栅极堆叠中的第一金属层上形成第二金属层并且在第二栅极堆叠中部分去除的第一金属层上，第二金属层具有第二功函数。

47. 发明授权

US07625791B2 High-k dielectric metal gate device structure and method for forming the same 有权
标题翻译：高k电介质金属栅极器件结构及其形成方法
公开(公告)号：US07625791B2
公开(公告)日：2009-12-01
申请号：US11926830
申请日：2007-10-29
申请人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
发明人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. A process for simultaneously forming the NMOS and PMOS gate structures includes forming the high-k gate dielectric material, and the work function tuning layer thereover, then selectively removing the work function tuning layer from the NMOS region and carrying out a plasma treatment to selectively dope the high-k gate dielectric material in the NMOS region with a dopant impurity while the high-k gate dielectric in the PMOS region is substantially free of the dopant impurity.
摘要翻译：金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。用于同时形成NMOS和PMOS栅极结构的工艺包括在其上形成高k栅极介电材料和功函数调谐层，然后从NMOS区选择性地去除功函数调谐层，并进行等离子体处理以选择性地掺杂具有掺杂剂杂质的NMOS区域中的高k栅极电介质材料，而PMOS区域中的高k栅极电介质基本上不含掺杂剂杂质。

48. 发明授权

US07435640B2 Method of fabricating gate structure 有权
标题翻译：栅极结构的制作方法
公开(公告)号：US07435640B2
公开(公告)日：2008-10-14
申请号：US11164025
申请日：2005-11-08
申请人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L21/8238
CPC分类号： H01L21/28202 , H01L21/28088 , H01L21/76822 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.
摘要翻译：提供一种制造栅极结构的方法。首先，在基板上形成牺牲氧化物层。进行氮化处理工艺以重新分配牺牲层和衬底中的氮原子，并产生浓度分布，使得氮的浓度逐渐增加，然后在牺牲氧化物层中具有氮的最大浓度朝向衬底减小。接下来，除去牺牲氧化物层。进行再氧化处理以在衬底的表面上产生界面层。在基板上依次形成高K（介电常数）栅介质层，阻挡层和金属层。限定金属层，势垒层，高K栅极介电层和界面层以形成层叠栅极结构。

49. 发明申请

US20080157231A1 GATE STRUCTURE 审中-公开
标题翻译：门结构
公开(公告)号：US20080157231A1
公开(公告)日：2008-07-03
申请号：US12046433
申请日：2008-03-11
申请人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L29/94
CPC分类号： H01L21/28202 , H01L21/28088 , H01L21/76822 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.
摘要翻译：提供一种制造栅极结构的方法。首先，在基板上形成牺牲氧化物层。进行氮化处理工艺以重新分配牺牲层和衬底中的氮原子，并产生浓度分布，使得氮的浓度逐渐增加，然后在牺牲氧化物层中具有氮的最大浓度朝向衬底减小。接下来，除去牺牲氧化物层。进行再氧化处理以在衬底的表面上产生界面层。在基板上依次形成高K（介电常数）栅介质层，阻挡层和金属层。限定金属层，势垒层，高K栅极介电层和界面层以形成层叠栅极结构。

50. 发明授权

US06455389B1 Method for preventing a by-product ion moving from a spacer 有权
标题翻译：防止副产物离子从间隔物移动的方法
公开(公告)号：US06455389B1
公开(公告)日：2002-09-24
申请号：US09872261
申请日：2001-06-01
申请人： Kuo-Tai Huang , Chao-Sheng Lin , Li-Wei Cheng
发明人： Kuo-Tai Huang , Chao-Sheng Lin , Li-Wei Cheng
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L29/4983 , H01L29/6656
摘要： This invention relates to a method that prevents by-productions from moving from a spacer. In particular by using an offset liner, a liner with a treated surface and a spacer that is formed by using the atomic layer deposition method or the rapid thermal chemical vapor deposition method. The present invention uses a liner, whose surface is treated, and a spacer, which is formed by using the atomic layer deposition method or the rapid thermal chemical vapor deposition method. This prevents by-product ions from moving from the spacer to other regions by using actions in diffusion and drift to affect the voltage stability of the semiconductor device after the current is connected. This defect will further affect qualities of the semiconductor device.
摘要翻译：本发明涉及防止副产物从间隔物移动的方法。特别是通过使用偏移衬垫，具有经处理的表面的衬垫和通过使用原子层沉积法或快速热化学气相沉积法形成的间隔物。本发明使用表面被处理的衬垫和使用原子层沉积法或快速热化学气相沉积法形成的间隔物。通过使用扩散和漂移中的动作来影响电流连接后的半导体器件的电压稳定性，防止副产物离子从间隔物移动到其它区域。该缺陷将进一步影响半导体器件的质量。

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