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1. 发明授权

US08324090B2 Method to improve dielectric quality in high-k metal gate technology 有权
标题翻译：提高高k金属栅极技术介质质量的方法
公开(公告)号：US08324090B2
公开(公告)日：2012-12-04
申请号：US12338787
申请日：2008-12-18
申请人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Yong-Tian Hou , Carlos H. Diaz
发明人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Yong-Tian Hou , Carlos H. Diaz
IPC分类号： H01L21/4763 , H01L25/11 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和金属层。

2. 发明申请

US20100052063A1 METHOD TO IMPROVE DIELECTRIC QUALITY IN HIGH-K METAL GATE TECHNOLOGY 有权
标题翻译：在高K金属门技术中提高介电质量的方法
公开(公告)号：US20100052063A1
公开(公告)日：2010-03-04
申请号：US12338787
申请日：2008-12-18
申请人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Carlos H. Diaz , Yong-Tian Hou
发明人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Carlos H. Diaz , Yong-Tian Hou
IPC分类号： H01L25/11 , H01L21/4763 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和金属层。

3. 发明申请

US20080258185A1 Semiconductor structure with dielectric-sealed doped region 有权
标题翻译：具有绝缘密封掺杂区域的半导体结构
公开(公告)号：US20080258185A1
公开(公告)日：2008-10-23
申请号：US11788226
申请日：2007-04-19
申请人： Huan-Tsung Huang , Kuo-Cheng Wu , Carlos H. Diaz
发明人： Huan-Tsung Huang , Kuo-Cheng Wu , Carlos H. Diaz
IPC分类号： H01L29/772 , H01L29/78
CPC分类号： H01L21/76232 , H01L29/0653 , H01L29/66636 , H01L29/66651
摘要： Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.
摘要翻译：泄漏电流可以通过形成密封电介质来代替源极/漏极区域和衬底材料之间的常规结点而大大减小。在用半导体材料填充沟槽之前，在衬底中形成沟槽，并且用密封电介质衬里。优选地，沟槽被过度填充，并且CMP工艺使过填充材料平坦化。如果需要，可以在平坦化之后在沟槽顶上生长外延层。

4. 发明授权

US07768072B2 Silicided metal gate for multi-threshold voltage configuration 有权
标题翻译：硅化金属栅极，用于多阈值电压配置
公开(公告)号：US07768072B2
公开(公告)日：2010-08-03
申请号：US11728809
申请日：2007-03-27
申请人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
发明人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
IPC分类号： H01L29/94
CPC分类号： H01L27/088 , H01L21/28097 , H01L21/82345 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.
摘要翻译：具有改进的功函数和良好的DIBL（漏极诱发的势垒降低）和SCE（短沟道效应）特性的低电压阈值MOSFET（MOS场效应晶体管）的PMOS（p沟道金属氧化物半导体）器件，以及一种方法用于制造这样的装置。 PMOS器件包括设置在衬底上并包括硅化栅电极的栅极结构。硅化物优选为富镍，并且包括在栅电极和将栅电极与衬底分离的电介质层之间的界面处或附近的峰值铂浓度。通过多步快速热退火或类似方法制备铂峰区域。 PMOS器件还可以包括两个这样的MOSFET，其中一个是硼掺杂的，其中一个不是。

5. 发明授权

US08415749B2 Semiconductor structure with dielectric-sealed doped region 有权
公开(公告)号：US08415749B2
公开(公告)日：2013-04-09
申请号：US11788226
申请日：2007-04-19
申请人： Huan-Tsung Huang , Kou-Cheng Wu , Carlos H. Diaz
发明人： Huan-Tsung Huang , Kou-Cheng Wu , Carlos H. Diaz
IPC分类号： H01L29/51
CPC分类号： H01L21/76232 , H01L29/0653 , H01L29/66636 , H01L29/66651
摘要： Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.

6. 发明申请

US20080237750A1 Silicided metal gate for multi-threshold voltage configuration 有权
标题翻译：硅化金属栅极，用于多阈值电压配置
公开(公告)号：US20080237750A1
公开(公告)日：2008-10-02
申请号：US11728809
申请日：2007-03-27
申请人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
发明人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L21/28097 , H01L21/82345 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.
摘要翻译：具有改进的功函数和良好的DIBL（漏极诱发的势垒降低）和SCE（短沟道效应）特性的低电压阈值MOSFET（MOS场效应晶体管）的PMOS（p沟道金属氧化物半导体）器件，以及一种方法用于制造这样的装置。 PMOS器件包括设置在衬底上并包括硅化栅电极的栅极结构。硅化物优选为富镍，并且包括在栅电极和将栅电极与衬底分离的电介质层之间的界面处或附近的峰值铂浓度。通过多步快速热退火或类似方法制备铂峰区域。 PMOS器件还可以包括两个这样的MOSFET，其中一个是硼掺杂的，其中一个不是。

7. 发明授权

US09595443B2 Metal gate structure of a semiconductor device 有权
标题翻译：半导体器件的金属栅极结构
公开(公告)号：US09595443B2
公开(公告)日：2017-03-14
申请号：US13277642
申请日：2011-10-20
申请人： Ming Zhu , Hui-Wen Lin , Harry-Hak-Lay Chuang , Bao-Ru Young , Yuan-Sheng Huang , Ryan Chia-Jen Chen , Chao-Cheng Chen , Kuo-Cheng Ching , Ting-Hua Hsieh , Carlos H. Diaz
发明人： Ming Zhu , Hui-Wen Lin , Harry-Hak-Lay Chuang , Bao-Ru Young , Yuan-Sheng Huang , Ryan Chia-Jen Chen , Chao-Cheng Chen , Kuo-Cheng Ching , Ting-Hua Hsieh , Carlos H. Diaz
IPC分类号： H01L21/70 , H01L21/28 , H01L21/8234 , H01L29/49 , H01L29/66 , H01L29/423
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823437 , H01L21/82345 , H01L21/823475 , H01L21/823481 , H01L29/42376 , H01L29/4966
摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.
摘要翻译：本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，包括围绕并分离P活性区域和N-有源区域的隔离区域; 在P-活性区域上的P金属栅电极，并且在隔离区域上延伸，其中P金属栅电极包括P功函数金属和P功函数金属与衬底之间的含氧TiN层; 以及N型金属栅电极，其在N-有源区上方并在隔离区上方延伸，其中N型金属栅电极包括N功函数金属和N功函数金属与衬底之间的富氮TiN层其中富氮TiN层在隔离区域上连接到含氧TiN层。

8. 发明授权

US08143680B2 Gated diode with non-planar source region 有权
标题翻译：具有非平面源极区域的栅极二极管
公开(公告)号：US08143680B2
公开(公告)日：2012-03-27
申请号：US12778912
申请日：2010-05-12
申请人： Da-Wen Lin , Ying-Shiou Lin , Shyh-Wei Wang , Li-Ping Huang , Ying-Keung Leung , Carlos H. Diaz
发明人： Da-Wen Lin , Ying-Shiou Lin , Shyh-Wei Wang , Li-Ping Huang , Ying-Keung Leung , Carlos H. Diaz
IPC分类号： H01L29/66 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7391 , H01L29/0657 , H01L29/42312 , H01L29/66356
摘要： A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.
摘要翻译：门控二极管半导体器件或类似部件及其制造方法。该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且与源极和漏极相邻。源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。如果两者都存在，则源极和漏极可以是对称的或非对称的。这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

9. 发明授权

US07342289B2 Strained silicon MOS devices 有权
标题翻译：应变硅MOS器件
公开(公告)号：US07342289B2
公开(公告)日：2008-03-11
申请号：US10637351
申请日：2003-08-08
申请人： Chien-Chao Huang , Chung-Hu Ge , Wen-Chin Lee , Chenming Hu , Carlos H. Diaz , Fu-Liang Yang
发明人： Chien-Chao Huang , Chung-Hu Ge , Wen-Chin Lee , Chenming Hu , Carlos H. Diaz , Fu-Liang Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.
摘要翻译：一种提高集成电路中MOS器件的载流子迁移率的结构。该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

10. 发明授权

US06368928B1 Method of forming an indium retrograde profile via use of a low temperature anneal procedure to reduce NMOS short channel effects 有权
标题翻译：通过使用低温退火工艺形成铟逆行曲线以减少NMOS短沟道效应的方法
公开(公告)号：US06368928B1
公开(公告)日：2002-04-09
申请号：US09878455
申请日：2001-06-12
申请人： Howard Chih-Hao Wang , Su-Yu Lu , Mu-Chi Chiang , Yu-Sen Chu , Chao-Jie Tsai , Carlos H. Diaz
发明人： Howard Chih-Hao Wang , Su-Yu Lu , Mu-Chi Chiang , Yu-Sen Chu , Chao-Jie Tsai , Carlos H. Diaz
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/1083
摘要： A method of forming an implanted pocket region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an initial indium pocket region, with an initial indium profile, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, a low temperature anneal procedure is used to activate indium ions in the initial indium pocket region, and to create a final indium pocket region, featuring a final indium profile. The final indium profile remains unchanged after experiencing subsequent high temperature procedures, such as a post-heavily doped, source/drain anneal. The narrow channel length NMOS devices, fabricated using the low temperature anneal procedure described in this invention, resulted in a reduced Vt roll-off phenomena, when compared to counterpart, narrow channel length NMOS, formed without the benefit of the low temperature anneal procedure.
摘要翻译：已经开发了形成注入口袋区域以减少窄沟道长度的信道效应（SCE）的方法，即NMOS器件。在形成具有初始铟分布的初始铟袋区域之后，在用于容纳N型源极/漏极区域的P型半导体区域中，使用低温退火程序来激活初始铟中的铟离子口袋区域，并创建最终的铟口袋区域，具有最终的铟型材。在经历随后的高温程序（例如重掺杂的源极/漏极退火）之后，最终的铟分布保持不变。使用本发明中描述的低温退火方法制造的窄沟道长度的NMOS器件，与对比的窄沟道长度NMOS相比，导致了减小的Vt滚降现象，而窄通道长度NMOS则不受低温退火工艺的影响。

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