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41. 发明授权

US08391095B2 Method controlling deep power down mode in multi-port semiconductor memory 有权
标题翻译：在多端口半导体存储器中控制深度掉电模式的方法
公开(公告)号：US08391095B2
公开(公告)日：2013-03-05
申请号：US12768060
申请日：2010-04-27
申请人： Ho-Cheol Lee , Jung-Bae Lee
发明人： Ho-Cheol Lee , Jung-Bae Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C5/144 , G11C5/147 , G11C8/16
摘要： Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.
摘要翻译：公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

42. 发明授权

US08154934B2 Semiconductor memory device and memory system having the same 有权
标题翻译：半导体存储器件和具有该半导体存储器件的存储器系统
公开(公告)号：US08154934B2
公开(公告)日：2012-04-10
申请号：US12788029
申请日：2010-05-26
申请人： Ho-Young Kim , Ho-Cheol Lee , Jung-Bae Lee
发明人： Ho-Young Kim , Ho-Cheol Lee , Jung-Bae Lee
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/222 , G11C2207/2272
摘要： A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.
摘要翻译：公开了一种半导体存储器件。半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号阵列并响应于内部时钟信号输出读取数据信号。半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号内部时钟信号。

43. 发明申请

US20110249483A1 STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE 有权
标题翻译：具有片间连接单元的堆叠存储器件，包括其的存储器系统以及传输线延迟时间补偿方法
公开(公告)号：US20110249483A1
公开(公告)日：2011-10-13
申请号：US13080061
申请日：2011-04-05
申请人： Chi-Sung Oh , Jin-Ho Kim , Ho-Cheol Lee , Uk-Song Kang , Hoon Lee
发明人： Chi-Sung Oh , Jin-Ho Kim , Ho-Cheol Lee , Uk-Song Kang , Hoon Lee
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C7/10 , G11C5/02 , G11C7/1048
摘要： A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.
摘要翻译：提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号传输线。层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

44. 发明申请

US20100232249A1 MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR 有权
标题翻译：具有可变存取码的多端口半导体存储器件及其方法
公开(公告)号：US20100232249A1
公开(公告)日：2010-09-16
申请号：US12785832
申请日：2010-05-24
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/16 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供一种具有可变访问路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

45. 发明申请

US20100109753A1 METHOD OF OUTPUTTING TEMPERATURE DATA IN SEMICONDUCTOR DEVICE AND TEMPERATURE DATA OUTPUT CIRCUIT THEREFOR 有权
标题翻译：在半导体器件中输出温度数据的方法及其温度数据输出电路
公开(公告)号：US20100109753A1
公开(公告)日：2010-05-06
申请号：US12605032
申请日：2009-10-23
申请人： YUN-YOUNG LEE , Kyu-Chan Lee , Ho-Cheol Lee
发明人： YUN-YOUNG LEE , Kyu-Chan Lee , Ho-Cheol Lee
IPC分类号： H01L37/00
CPC分类号： G01K7/015 , G01K2219/00
摘要： A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation.
摘要翻译：提供了一种在半导体器件和温度数据输出电路中输出温度数据的方法。响应于响应于上电信号而被激活的引导使能信号而产生脉冲信号，并且响应于上电操作期间的模式设置信号而使生成失效。通过将与温度无关的参考电压与随温度变化而变化的感测电压进行比较，响应于脉冲信号产生比较信号。响应于比较信号来改变温度数据。因此，温度数据输出电路可以快速输出在上电操作期间测量的半导体器件的精确温度。

46. 发明授权

US07394711B2 Multi-port semiconductor memory device and method for accessing and refreshing the same 失效
标题翻译：多端口半导体存储器件及其访问和刷新方法
公开(公告)号：US07394711B2
公开(公告)日：2008-07-01
申请号：US11616846
申请日：2006-12-27
申请人： Chi-Sung Oh , Ho-Cheol Lee , Nam-Jong Kim
发明人： Chi-Sung Oh , Ho-Cheol Lee , Nam-Jong Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1075 , G11C8/10 , G11C8/12 , G11C11/40603 , G11C11/40618
摘要： A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.
摘要翻译：提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

47. 发明申请

US20050194664A1 Bonding pad arrangement method for semiconductor devices 审中-公开
公开(公告)号：US20050194664A1
公开(公告)日：2005-09-08
申请号：US11107897
申请日：2005-04-18
申请人： Ho-Cheol Lee , Jae-Hoon Kim , Jung-Su Ryu
发明人： Ho-Cheol Lee , Jae-Hoon Kim , Jung-Su Ryu
IPC分类号： H01L21/60 , H01L23/50 , H01L23/495
CPC分类号： H01L24/06 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/48472 , H01L2224/4912 , H01L2224/49171 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , Y10T29/49121 , H01L2224/45099 , H01L2924/00
摘要： A variety of pad arrangements are provided for semiconductor devices for reducing the likelihood of bonding failures, particularly those due to shorts, and/or for reducing the difference in length between bonding wires to decrease signal skew during operation of the semiconductor device and improve signal integrity.

48. 发明授权

US5838990A Circuit in a semiconductor memory for programming operation modes of the memory 失效
标题翻译：用于存储器的编程操作模式的半导体存储器中的电路
公开(公告)号：US5838990A
公开(公告)日：1998-11-17
申请号：US905562
申请日：1997-08-04
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G06F9/00 , G06F13/16
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

49. 发明授权

US5835956A Synchronous dram having a plurality of latency modes 失效
标题翻译：具有多个等待时间模式的同步电话
公开(公告)号：US5835956A
公开(公告)日：1998-11-10
申请号：US822148
申请日：1997-03-17
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G06F13/16
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

50. 发明授权

US5703828A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5703828A
公开(公告)日：1997-12-30
申请号：US580622
申请日：1995-12-29
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

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