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    • 41. 发明授权
    • Advanced MRAM design
    • 先进的MRAM设计
    • US07719882B2
    • 2010-05-18
    • US11743453
    • 2007-05-02
    • Wen-Chin LinHsu-Chen ChengYu-Jen WangDenny Tang
    • Wen-Chin LinHsu-Chen ChengYu-Jen WangDenny Tang
    • G11C11/00
    • G11C11/16G11C11/005H01L2924/0002H01L2924/00
    • Disclosed herein is a technique for created an advanced MRAM array for constructing a memory integrated circuit chip. More specifically, the disclosed principles provide for an integrated circuit memory chip comprised of a combination of at least one of an array of high-speed magnetic memory cells, and at least one of an array of high-density magnetic memory cells. Accordingly, a memory chip constructed as disclosed herein provides the benefit of both high-speed and high-density memory cells on the same memory chip. As a result, applications benefiting from the use of (or perhaps even needing) high-speed memory cells are provided by the memory cells in the high-speed memory cell array.
    • 这里公开了一种用于创建用于构建存储器集成电路芯片的高级MRAM阵列的技术。 更具体地,所公开的原理提供了由高速磁存储器单元的阵列中的至少一个和高密度磁存储单元的阵列中的至少一个的组合构成的集成电路存储器芯片。 因此,如本文所公开的构造的存储器芯片提供了在相同存储器芯片上的高速和高密度存储器单元的益处。 结果,受益于使用(或甚至需要的)高速存储器单元的应用由高速存储单元阵列中的存储单元提供。
    • 43. 发明授权
    • Magnetoresistive random access memory device with small-angle toggle write lines
    • 具有小角度切换写入线的磁阻随机存取存储器件
    • US07599215B2
    • 2009-10-06
    • US11840051
    • 2007-08-16
    • Wen-Chin LinDenny TangHsu Chen Cheng
    • Wen-Chin LinDenny TangHsu Chen Cheng
    • G11C11/15
    • G11C11/16
    • Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.
    • 这里公开了具有小角度切换写入线的触发模式磁阻随机存取存储器(MRAM)器件以及触发模式切换MRAM器件的相关方法。 还公开了根据所公开的原理构造的MRAM装置的布局。 一般来说,所公开的原理提供用于切换切换模式MRAM器件的非正交对准的触发模式写入线,其使用偏置场来降低切换每个器件的磁状态所需的阈值。 虽然常规的切换模式写入线提供所施加的磁场的期望的正交取向以优化器件切换,但偏置场的使用影响该正交取向。 如本文所公开的,通过非正交对准这两个写入线,可以补偿偏置场的有害影响,使得如所期望的那样,施加到两条线的器件的净场也基本正交。
    • 45. 发明授权
    • Magnetoresistive structures and fabrication methods
    • 磁阻结构和制造方法
    • US07443638B2
    • 2008-10-28
    • US10907974
    • 2005-04-22
    • Yu-Jen WangChih-Huang LaiWen-Chin LinDenny TangChao-Hsiung Wang
    • Yu-Jen WangChih-Huang LaiWen-Chin LinDenny TangChao-Hsiung Wang
    • G11B5/39G11B5/33
    • G11B5/3929B82Y10/00G11B2005/3996
    • Disclosed herein is a magnetoresistive structure, for example useful as a spin-valve or GMR stack in a magnetic sensor, and a fabrication method thereof. The magnetoresistive structure uses twisted coupling to induce a perpendicular magnetization alignment between the free layer and the pinned layer. Ferromagnetic layers of the free and pinned layers are exchange-coupled using antiferromagnetic layers having substantially parallel exchange-biasing directions. Thus, embodiments can be realized that have antiferromagnetic layers formed of a same material and/or having a same blocking temperature. At least one of the free and pinned layers further includes a second ferromagnetic layer and an insulating layer, such as a NOL, between the two ferromagnetic layers. The insulating layer causes twisted coupling between the two ferromagnetic layers, rotating the magnetization direction of one 90 degrees relative to the magnetization direction of the other.
    • 这里公开了一种例如在磁传感器中用作自旋阀或GMR堆叠的磁阻结构及其制造方法。 磁阻结构使用扭转耦合来引起自由层和被钉扎层之间的垂直磁化对准。 使用具有基本平行的交换偏压方向的反铁磁层来交换耦合自由和被钉扎层的铁磁层。 因此,可以实现具有由相同材料形成的反铁磁层和/或具有相同阻挡温度的实施例。 自由和被钉扎层中的至少一个还包括在两个铁磁层之间的第二铁磁层和绝缘层,例如NOL。 绝缘层引起两个铁磁层之间的扭转耦合,使相对于另一个的磁化方向旋转90度的磁化方向。
    • 47. 发明授权
    • System and method for passing high energy particles through a mask
    • 将高能粒子通过掩模的系统和方法
    • US07151271B2
    • 2006-12-19
    • US10681541
    • 2003-10-08
    • Chao-Hsiung WangDenny TangWen-Chin LinLi-Shyue Lai
    • Chao-Hsiung WangDenny TangWen-Chin LinLi-Shyue Lai
    • A61N5/00G21G5/00
    • H01J37/3174B82Y10/00B82Y40/00
    • A method and system is disclosed for concentrating high energy particles on a predetermined area on a target semiconductor substrate. A high energy source for generating a predetermined amount of high energy particles, and an electro-magnetic radiation source for generating low energy beams are used together. The system also uses a mask set having at least one mask with at least one alignment area and at least one mask target area thereon, the mask target area passing more high energy particles then any other area of the mask. At least one protection shield is incorporated in the system for protecting the alignment area from being exposed to the high energy particles, wherein the mask is aligned with the predetermined target semiconductor substrate by passing the low energy beams through the alignment area, wherein the high energy particles generated by the high energy source pass through the mask target area to land on the predetermined area on the target semiconductor substrate.
    • 公开了一种用于将高能粒子集中在目标半导体衬底上的预定区域上的方法和系统。 用于产生预定量的高能粒子的高能量源和用于产生低能量束的电磁辐射源一起使用。 该系统还使用具有至少一个具有至少一个对准区域和至少一个掩模目标区域的掩模的掩模组,掩模目标区域通过更多的高能粒子,然后通过掩模的任何其它区域。 至少一个保护屏蔽被并入系统中,用于保护对准区域不暴露于高能粒子,其中通过使低能量束通过对准区域,掩模与预定目标半导体衬底对齐,其中高能量 由高能量源产生的粒子通过掩模对象区域落在目标半导体衬底上的预定区域上。
    • 50. 发明授权
    • Reference generator for multilevel nonlinear resistivity memory storage elements
    • 多电平非线性电阻率存储元件的参考发生器
    • US06985383B2
    • 2006-01-10
    • US10689421
    • 2003-10-20
    • Denny D. TangWen-Chin Lin
    • Denny D. TangWen-Chin Lin
    • G11C11/14G11C11/15G11C7/14
    • G11C5/147G11C11/16G11C11/1673G11C11/1675G11C11/5607G11C2211/5634
    • A multilevel reference generator has a plurality of nonlinear standard resistive elements where each resistive element is biased at a constant level to develop a resultant level. The multilevel reference generator has a plurality of mirror sources. Each mirror source is in communication with the one of the plurality of resistive elements such that each mirror source receives the resultant level from the one standard resistive element and provides a mirrored replication of the resultant level. The multilevel reference generator has a plurality of reference level combining circuits. The reference level combining circuit includes a resultant level summing circuit that additively combines the first and second mirrored replication level and a level scaling circuit to create a scaling of the combined first and second mirrored replication levels to create the reference level.
    • 多电平参考发生器具有多个非线性标准电阻元件,其中每个电阻元件被偏置在恒定电平以产生合成电平。 多电平参考发生器具有多个镜源。 每个反射镜源与多个电阻元件中的一个电阻元件相通,使得每个反射镜源从一个标准电阻元件接收合成电平,并提供所得电平的镜像复制。 多电平参考发生器具有多个参考电平组合电路。 参考电平组合电路包括相加地组合第一和第二镜像复制级别的电平求和电路和级别缩放电路,以创建组合的第一和第二镜像复制级别的缩放以创建参考电平。