专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07205632B2 Anti-scattering attenuator structure for high energy particle radiation into integrated circuits 有权
标题翻译：抗散射衰减器结构，用于高能粒子辐射成集成电路
公开(公告)号：US07205632B2
公开(公告)日：2007-04-17
申请号：US10818009
申请日：2004-04-05
申请人： Wen-Chin Lin , Denny D. Tang , Chao-Hsiung Wang
发明人： Wen-Chin Lin , Denny D. Tang , Chao-Hsiung Wang
IPC分类号： H01L29/00
CPC分类号： H01L21/263 , H01L27/0688 , H01L27/08
摘要： A microelectronics device including a semiconductor device located at least partially over a substrate, a bombarded area located at least partially over the substrate and adjacent the semiconductor device, and a bombarded attenuator interposing the semiconductor device and the bombarded area.
摘要翻译：一种微电子器件，包括至少部分地位于衬底上的半导体器件，至少部分地位于衬底上并且邻近半导体器件的轰击区域，以及插入半导体器件和被轰击区域的轰击衰减器。

2. 发明授权

US07173846B2 Magnetic RAM and array architecture using a two transistor, one MTJ cell 有权
标题翻译：磁性RAM和阵列架构使用两个晶体管，一个MTJ单元
公开(公告)号：US07173846B2
公开(公告)日：2007-02-06
申请号：US10366499
申请日：2003-02-13
申请人： Wen-Chin Lin , Denny D. Tang , Yu Der Chih
发明人： Wen-Chin Lin , Denny D. Tang , Yu Der Chih
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A new magnetic RAM cell device is achieved. The device comprisese, first, a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A reading switch is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.
摘要翻译：实现了新的磁性RAM单元装置。该装置首先包括由电介质层分离的自由层和钉扎层的MTJ电池。读取开关耦合在自由层和读取线之间。写入开关耦合在固定层的第一端和第一写入线之间。固定层的第二端耦合到第二写入线。公开了使用MRAM单元的架构。

3. 发明授权

US07166881B2 Multi-sensing level MRAM structures 有权
标题翻译：多感测级MRAM结构
公开(公告)号：US07166881B2
公开(公告)日：2007-01-23
申请号：US10685824
申请日：2004-08-23
申请人： Wen Chin Lin , Denny D. Tang , Chien-Chung Hung
发明人： Wen Chin Lin , Denny D. Tang , Chien-Chung Hung
IPC分类号： H01L29/76
CPC分类号： G11C11/15 , G11C11/5607 , G11C2211/5615 , H01L27/228
摘要： The present disclosure provides an improved magnetic memory cell. The magnetic memory cell includes a switching element and two magnetic tunnel junction (MTJ) devices. A conductor connects the first and second MTJ devices in a parallel configuration, and serially connecting the parallel configuration to an electrode of the switching element. The resistance of the first MTJ device is different from the resistance of the second.
摘要翻译：本公开提供了一种改进的磁存储单元。磁存储单元包括开关元件和两个磁性隧道结（MTJ）器件。导体以并联结构连接第一和第二MTJ装置，并且将并联配置串联连接到开关元件的电极。第一台MTJ装置的电阻不同于第二台的电阻。

4. 发明授权

US07099176B2 Non-orthogonal write line structure in MRAM 有权
标题翻译： MRAM中的非正交写行结构
公开(公告)号：US07099176B2
公开(公告)日：2006-08-29
申请号：US10827079
申请日：2004-04-19
申请人： Wen Chin Lin , Denny D. Tang , Li-Shyue Lai
发明人： Wen Chin Lin , Denny D. Tang , Li-Shyue Lai
IPC分类号： G11C5/08
CPC分类号： G11C11/16
摘要： An MRAM cell including an MRAM cell stack located over a substrate and first and second write lines spanning at least one side of the MRAM cell stack and defining a projected region of intersection of the MRAM cell stack and the first and second write lines. The MRAM cell stack includes a pinned layer, a tunneling barrier layer, and a free layer, the tunneling barrier layer interposing the pinned layer and the free layer. The first write line extends in a first direction within the projected region of intersection. The second write line extends in a second direction within the projected region of intersection. The first and second directions are angularly offset by an angle ranging between 45 and 90 degrees, exclusively. At least one write line may be perpendicular to the easy axis of free layer, while the other line may be rotated off the easy axis of the free layer by an angle which is larger than zero, such as to compensate for a shifting astroid curve.
摘要翻译： MRAM单元包括位于衬底上的MRAM单元堆叠，以及横跨MRAM单元堆叠的至少一侧的第一和第二写入线，并且定义MRAM单元堆叠与第一和第二写入线之间的投影区域。 MRAM单元堆叠包括钉扎层，隧道势垒层和自由层，隧道势垒层插入被钉扎层和自由层。第一写入线在投影的交叉区域内沿第一方向延伸。第二写入线在投影的交叉区域内沿第二方向延伸。第一和第二方向的角度偏移45度到90度之间的角度。至少一条写入线可以垂直于自由层的容易轴，而另一条线可以从自由层的容易轴旋转大于零的角度，以补偿移动的星形曲线。

5. 发明授权

US06985383B2 Reference generator for multilevel nonlinear resistivity memory storage elements 失效
标题翻译：多电平非线性电阻率存储元件的参考发生器
公开(公告)号：US06985383B2
公开(公告)日：2006-01-10
申请号：US10689421
申请日：2003-10-20
申请人： Denny D. Tang , Wen-Chin Lin
发明人： Denny D. Tang , Wen-Chin Lin
IPC分类号： G11C11/14 , G11C11/15 , G11C7/14
CPC分类号： G11C5/147 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/5607 , G11C2211/5634
摘要： A multilevel reference generator has a plurality of nonlinear standard resistive elements where each resistive element is biased at a constant level to develop a resultant level. The multilevel reference generator has a plurality of mirror sources. Each mirror source is in communication with the one of the plurality of resistive elements such that each mirror source receives the resultant level from the one standard resistive element and provides a mirrored replication of the resultant level. The multilevel reference generator has a plurality of reference level combining circuits. The reference level combining circuit includes a resultant level summing circuit that additively combines the first and second mirrored replication level and a level scaling circuit to create a scaling of the combined first and second mirrored replication levels to create the reference level.
摘要翻译：多电平参考发生器具有多个非线性标准电阻元件，其中每个电阻元件被偏置在恒定电平以产生合成电平。多电平参考发生器具有多个镜源。每个反射镜源与多个电阻元件中的一个电阻元件相通，使得每个反射镜源从一个标准电阻元件接收合成电平，并提供所得电平的镜像复制。多电平参考发生器具有多个参考电平组合电路。参考电平组合电路包括相加地组合第一和第二镜像复制级别的电平求和电路和级别缩放电路，以创建组合的第一和第二镜像复制级别的缩放以创建参考电平。

6. 发明授权

US06909628B2 High density magnetic RAM and array architecture using a one transistor, one diode, and one MTJ cell 有权
标题翻译：使用一个晶体管，一个二极管和一个MTJ单元的高密度磁性RAM和阵列架构
公开(公告)号：US06909628B2
公开(公告)日：2005-06-21
申请号：US10366498
申请日：2003-02-13
申请人： Wen-Chin Lin , Denny D. Tang , Yu Der Chih
发明人： Wen-Chin Lin , Denny D. Tang , Yu Der Chih
IPC分类号： G11C11/00 , G11C11/15 , G11C11/16 , H01L43/00 , H03K5/02
CPC分类号： G11C11/16
摘要： A new magnetic RAM cell device is achieved. The device comprises a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A diode is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.
摘要翻译：实现了新的磁性RAM单元装置。该器件包括MTJ电池，其包括由电介质层分离的自由层和钉扎层。二极管耦合在自由层和读取线之间。写入开关耦合在固定层的第一端和第一写入线之间。固定层的第二端耦合到第二写入线。公开了使用MRAM单元的架构。

7. 发明授权

US07170775B2 MRAM cell with reduced write current 有权
标题翻译：降低写入电流的MRAM单元
公开(公告)号：US07170775B2
公开(公告)日：2007-01-30
申请号：US11030453
申请日：2005-01-06
申请人： Wen Chin Lin , Denny D. Tang , Li-Shyue Lai
发明人： Wen Chin Lin , Denny D. Tang , Li-Shyue Lai
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C5/063
摘要： A magnetic random access memory (MRAM) cell that includes an MRAM stack and a conductive line for carrying write current associated with the MRAM cell. The conductive line is oriented in a direction that is angularly offset from an easy axis of the MRAM stack by an acute angle, such as about 45 degrees.
摘要翻译：磁性随机存取存储器（MRAM）单元，其包括用于承载与MRAM单元相关联的写入电流的MRAM堆叠和导线。导线沿着与MRAM堆叠的容易轴成角度偏移的方向定向为锐角，例如约45度。

8. 发明授权

US6046109A Creation of local semi-insulating regions on semiconductor substrates 失效
标题翻译：在半导体衬底上形成局部半绝缘区域
公开(公告)号：US6046109A
公开(公告)日：2000-04-04
申请号：US998734
申请日：1997-12-29
申请人： Chungpin Liao , Denny D. Tang , Shin-Chii Lu
发明人： Chungpin Liao , Denny D. Tang , Shin-Chii Lu
IPC分类号： B01J19/12 , H01L21/263 , H01L21/265 , H01L21/322 , H01L21/76 , H01L27/08 , H01L21/302
CPC分类号： H01L21/76 , H01L21/263 , H01L21/26506 , H01L21/3221
摘要： The present invention solves the problem of how to form local regions of semi-insulating material within a single crystal substrate. It does this by irradiating the semiconductor with a high energy beam capable of producing radiation damage along its path. As a consequence of such radiation damage the resistivity of the semiconductor in the irradiated area is increased by several orders of magnitude, causing it to become semi-insulating. Semi-insulating regions of this type are effective as electrically isolating regions and can be used, for example, to decouple analog from digital circuits or to maintain high Q in integrated inductors after these devices have been made. The radiation used could be electromagnetic (such as X-rays or gamma rays) or it could comprise energetic particles such as protons, deuterons, etc. Confinement of the beam to local regions within the semiconductor is accomplished by means of suitable masks.
摘要翻译：本发明解决了如何在单晶衬底内形成半绝缘材料的局部区域的问题。它通过用能够沿其路径产生辐射损伤的高能量束照射半导体来实现。作为这种辐射损伤的结果，照射区域中的半导体的电阻率增加几个数量级，导致其变成半绝缘。这种类型的半绝缘区域作为电绝缘区域是有效的，并且可以用于例如在模拟器件被制造之后，使模拟与数字电路分离或者在集成电感器中保持高Q。所使用的辐射可以是电磁的（例如X射线或γ射线），或者它可以包括能量粒子，例如质子，氘核等。通过合适的掩模实现束到半导体内的局部区域的限制。

9. 发明授权

US5106767A Process for fabricating low capacitance bipolar junction transistor 失效
标题翻译：制造低电容双极结型晶体管的工艺
公开(公告)号：US5106767A
公开(公告)日：1992-04-21
申请号：US683408
申请日：1991-04-10
申请人： Janes H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
发明人： Janes H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
IPC分类号： H01L21/285 , H01L21/331 , H01L21/762
CPC分类号： H01L29/66287 , H01L21/28525 , H01L21/76229 , H01L29/66242 , Y10S148/102 , Y10S148/117 , Y10S148/124
摘要： This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferably polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.
摘要翻译：本发明涉及一种双极晶体管，其在升高的基极方面包含发射极，集电极基座以及所有这些基底都是自对准的内在和外在基极。本发明还涉及一种用于制造这样的器件的方法，其使用单个光刻和掩蔽步骤获得上述元件的自对准。晶体管的结构除了具有自嵌入元件之外，还包括复合介电隔离层，其不仅允许在器件制造期间执行多种功能，而且还可以在器件操作期间提供期望的电特性。复合隔离层由邻近半导体表面的氧化物层组成; 氧化物层上的氮化物层和该器件的最终结构中的氮化物层上的氧化物层。最后提到的氧化物层在制造过程的早期开始为可氧化材料层，优选多晶硅，其在该工艺的后续步骤中用作其未氧化状态的蚀刻停止，并且作为存储元件和掩模当自对准基准元件被去除并且必须去除这样暴露的下面的介质元件以提供平面发射器开口时，其氧化态。所产生的晶体管包括平面的发射极 - 发射极接触界面，其提供对底层本征基极区域的发射极深度的精细控制。

10. 发明授权

US4446476A Integrated circuit having a sublayer electrical contact and fabrication thereof 失效
标题翻译：具有子层电接触及其制造的集成电路
公开(公告)号：US4446476A
公开(公告)日：1984-05-01
申请号：US279119
申请日：1981-06-30
申请人： Randall D. Isaac , Tak H. Ning , Denny D. Tang
发明人： Randall D. Isaac , Tak H. Ning , Denny D. Tang
IPC分类号： H01L27/10 , H01L21/3205 , H01L21/331 , H01L21/74 , H01L21/76 , H01L21/762 , H01L21/8242 , H01L23/52 , H01L23/535 , H01L27/108 , H01L29/06 , H01L29/73 , H01L23/48 , H01L27/12 , H01L29/46 , H01L29/62
CPC分类号： H01L21/76237 , H01L21/743 , H01L21/76202 , H01L23/535 , H01L29/0638 , H01L2924/0002
摘要： An integrated circuit containing a refractory metallic silicide beneath a field isolation region and in electrical contact with electrical conductive regions of active impurity dopants in a semiconductive substrate; and process for the fabrication thereof.
摘要翻译：一种集成电路，其包含位于场隔离区下方的难熔金属硅化物，并与半导体衬底中的有源杂质掺杂物的导电区电接触; 及其制造方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式