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    • 3. 发明授权
    • Non-orthogonal write line structure in MRAM
    • MRAM中的非正交写行结构
    • US07099176B2
    • 2006-08-29
    • US10827079
    • 2004-04-19
    • Wen Chin LinDenny D. TangLi-Shyue Lai
    • Wen Chin LinDenny D. TangLi-Shyue Lai
    • G11C5/08
    • G11C11/16
    • An MRAM cell including an MRAM cell stack located over a substrate and first and second write lines spanning at least one side of the MRAM cell stack and defining a projected region of intersection of the MRAM cell stack and the first and second write lines. The MRAM cell stack includes a pinned layer, a tunneling barrier layer, and a free layer, the tunneling barrier layer interposing the pinned layer and the free layer. The first write line extends in a first direction within the projected region of intersection. The second write line extends in a second direction within the projected region of intersection. The first and second directions are angularly offset by an angle ranging between 45 and 90 degrees, exclusively. At least one write line may be perpendicular to the easy axis of free layer, while the other line may be rotated off the easy axis of the free layer by an angle which is larger than zero, such as to compensate for a shifting astroid curve.
    • MRAM单元包括位于衬底上的MRAM单元堆叠,以及横跨MRAM单元堆叠的至少一侧的第一和第二写入线,并且定义MRAM单元堆叠与第一和第二写入线之间的投影区域。 MRAM单元堆叠包括钉扎层,隧道势垒层和自由层,隧道势垒层插入被钉扎层和自由层。 第一写入线在投影的交叉区域内沿第一方向延伸。 第二写入线在投影的交叉区域内沿第二方向延伸。 第一和第二方向的角度偏移45度到90度之间的角度。 至少一条写入线可以垂直于自由层的容易轴,而另一条线可以从自由层的容易轴旋转大于零的角度,以补偿移动的星形曲线。
    • 5. 发明授权
    • Reference generator for multilevel nonlinear resistivity memory storage elements
    • 多电平非线性电阻率存储元件的参考发生器
    • US06985383B2
    • 2006-01-10
    • US10689421
    • 2003-10-20
    • Denny D. TangWen-Chin Lin
    • Denny D. TangWen-Chin Lin
    • G11C11/14G11C11/15G11C7/14
    • G11C5/147G11C11/16G11C11/1673G11C11/1675G11C11/5607G11C2211/5634
    • A multilevel reference generator has a plurality of nonlinear standard resistive elements where each resistive element is biased at a constant level to develop a resultant level. The multilevel reference generator has a plurality of mirror sources. Each mirror source is in communication with the one of the plurality of resistive elements such that each mirror source receives the resultant level from the one standard resistive element and provides a mirrored replication of the resultant level. The multilevel reference generator has a plurality of reference level combining circuits. The reference level combining circuit includes a resultant level summing circuit that additively combines the first and second mirrored replication level and a level scaling circuit to create a scaling of the combined first and second mirrored replication levels to create the reference level.
    • 多电平参考发生器具有多个非线性标准电阻元件,其中每个电阻元件被偏置在恒定电平以产生合成电平。 多电平参考发生器具有多个镜源。 每个反射镜源与多个电阻元件中的一个电阻元件相通,使得每个反射镜源从一个标准电阻元件接收合成电平,并提供所得电平的镜像复制。 多电平参考发生器具有多个参考电平组合电路。 参考电平组合电路包括相加地组合第一和第二镜像复制级别的电平求和电路和级别缩放电路,以创建组合的第一和第二镜像复制级别的缩放以创建参考电平。
    • 8. 发明授权
    • Creation of local semi-insulating regions on semiconductor substrates
    • 在半导体衬底上形成局部半绝缘区域
    • US6046109A
    • 2000-04-04
    • US998734
    • 1997-12-29
    • Chungpin LiaoDenny D. TangShin-Chii Lu
    • Chungpin LiaoDenny D. TangShin-Chii Lu
    • B01J19/12H01L21/263H01L21/265H01L21/322H01L21/76H01L27/08H01L21/302
    • H01L21/76H01L21/263H01L21/26506H01L21/3221
    • The present invention solves the problem of how to form local regions of semi-insulating material within a single crystal substrate. It does this by irradiating the semiconductor with a high energy beam capable of producing radiation damage along its path. As a consequence of such radiation damage the resistivity of the semiconductor in the irradiated area is increased by several orders of magnitude, causing it to become semi-insulating. Semi-insulating regions of this type are effective as electrically isolating regions and can be used, for example, to decouple analog from digital circuits or to maintain high Q in integrated inductors after these devices have been made. The radiation used could be electromagnetic (such as X-rays or gamma rays) or it could comprise energetic particles such as protons, deuterons, etc. Confinement of the beam to local regions within the semiconductor is accomplished by means of suitable masks.
    • 本发明解决了如何在单晶衬底内形成半绝缘材料的局部区域的问题。 它通过用能够沿其路径产生辐射损伤的高能量束照射半导体来实现。 作为这种辐射损伤的结果,照射区域中的半导体的电阻率增加几个数量级,导致其变成半绝缘。 这种类型的半绝缘区域作为电绝缘区域是有效的,并且可以用于例如在模拟器件被制造之后,使模拟与数字电路分离或者在集成电感器中保持高Q。 所使用的辐射可以是电磁的(例如X射线或γ射线),或者它可以包括能量粒子,例如质子,氘核等。通过合适的掩模实现束到半导体内的局部区域的限制。
    • 9. 发明授权
    • Process for fabricating low capacitance bipolar junction transistor
    • 制造低电容双极结型晶体管的工艺
    • US5106767A
    • 1992-04-21
    • US683408
    • 1991-04-10
    • Janes H. ComfortTze-Chiang ChenPong-Fei LuBernard S. MeyersonYuan-Chen SunDenny D. Tang
    • Janes H. ComfortTze-Chiang ChenPong-Fei LuBernard S. MeyersonYuan-Chen SunDenny D. Tang
    • H01L21/285H01L21/331H01L21/762
    • H01L29/66287H01L21/28525H01L21/76229H01L29/66242Y10S148/102Y10S148/117Y10S148/124
    • This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferably polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.
    • 本发明涉及一种双极晶体管,其在升高的基极方面包含发射极,集电极基座以及所有这些基底都是自对准的内在和外在基极。 本发明还涉及一种用于制造这样的器件的方法,其使用单个光刻和掩蔽步骤获得上述元件的自对准。 晶体管的结构除了具有自嵌入元件之外,还包括复合介电隔离层,其不仅允许在器件制造期间执行多种功能,而且还可以在器件操作期间提供期望的电特性。 复合隔离层由邻近半导体表面的氧化物层组成; 氧化物层上的氮化物层和该器件的最终结构中的氮化物层上的氧化物层。 最后提到的氧化物层在制造过程的早期开始为可氧化材料层,优选多晶硅,其在该工艺的后续步骤中用作其未氧化状态的蚀刻停止,并且作为存储元件和掩模 当自对准基准元件被去除并且必须去除这样暴露的下面的介质元件以提供平面发射器开口时,其氧化态。 所产生的晶体管包括平面的发射极 - 发射极接触界面,其提供对底层本征基极区域的发射极深度的精细控制。