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41. 发明申请

US20100214844A1 Memory system and programming method thereof 有权
标题翻译：存储器系统及其编程方法
公开(公告)号：US20100214844A1
公开(公告)日：2010-08-26
申请号：US12656083
申请日：2010-01-15
申请人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
发明人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642
摘要： Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage.
摘要翻译：提供了一种非易失性存储器系统及其编程方法。非易失性存储器系统的编程方法包括：参考要写入被配置为为所选存储器单元提供干扰的干扰单元的程序数据来调整所选择的存储器单元的编程验证电压，并根据调整后的程序验证电压。

42. 发明申请

US20100124119A1 Nonvolatile Memory Device and Read Methods Thereof 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US20100124119A1
公开(公告)日：2010-05-20
申请号：US12607518
申请日：2009-10-28
申请人： Changhyun Lee , Jungdal Choi , Byeong-In Choi
发明人： Changhyun Lee , Jungdal Choi , Byeong-In Choi
IPC分类号： G11C16/04 , G11C5/14
CPC分类号： G11C8/08 , G11C11/5642 , G11C16/3418 , G11C29/00
摘要： An object of the present inventive concept is providing a nonvolatile memory device having improved reliability by compensating a threshold voltage of a flash memory cell.A nonvolatile memory device according to the present inventive concept includes a memory cell array connected to a plurality of word lines; and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to an unselect word line among the plurality of word lines when a read operation is performed. The voltage generator generates the unselect read voltage having a different level according to whether the unselect word line is adjacent to the select word line or not.A nonvolatile memory device according to the present inventive concept compensates a threshold voltage increased or decreased due to various causes. According to the present inventive concept, reliability of a nonvolatile memory device is improved.
摘要翻译：本发明构思的目的是通过补偿闪存单元的阈值电压来提供具有改善的可靠性的非易失性存储器件。根据本发明构思的非易失性存储器件包括连接到多个字线的存储单元阵列; 以及电压发生器，用于当执行读取操作时，将选择读取电压提供给选择字线和取消选择读取电压到多个字线中的未选择字线。电压发生器根据取消选择字线是否与选择字线相邻而产生具有不同电平的取消读取电压。根据本发明构思的非易失性存储器件补偿由于各种原因而增加或减少的阈值电压。根据本发明构思，提高了非易失性存储装置的可靠性。

43. 发明申请

US20160180929A1 Variable Resistance Memory Device 有权
标题翻译：可变电阻存储器件
公开(公告)号：US20160180929A1
公开(公告)日：2016-06-23
申请号：US14955789
申请日：2015-12-01
申请人： YounSeon Kang , Jungdal Choi , Masayuki Terai , Youngbae Kim , Jung Moo Lee , Seungjae Jung
发明人： YounSeon Kang , Jungdal Choi , Masayuki Terai , Youngbae Kim , Jung Moo Lee , Seungjae Jung
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C7/00 , G11C8/00 , G11C11/16 , G11C11/1659 , G11C2213/71 , G11C2213/72 , H01L27/224 , H01L27/2409 , H01L27/2481
摘要： A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.
摘要翻译：可变电阻存储器件包括衬底上的上部互连，设置在衬底和上部互连之间并且彼此垂直间隔开的第一和第二字线，设置在第一和第二字线之间并与第一和第二字线相交的第一位线第二字线，设置在第一字线和第一位线的交叉区域中的存储单元以及第二字线和第一位线的相交区域，将第一字线直接连接到相应的第一字线上部互连中的一个，以及将第二字线直接连接到上部互连中的相应一个的第二字线接触。

44. 发明授权

US09111617B2 Three-dimensional semiconductor memory device 有权
标题翻译：三维半导体存储器件
公开(公告)号：US09111617B2
公开(公告)日：2015-08-18
申请号：US13585963
申请日：2012-08-15
申请人： Sunil Shim , Jang-gn Yun , Jeonghyuk Choi , Kwang Soo Seol , Jaehoon Jang , Jungdal Choi
发明人： Sunil Shim , Jang-gn Yun , Jeonghyuk Choi , Kwang Soo Seol , Jaehoon Jang , Jungdal Choi
IPC分类号： H01L29/78 , G11C16/04 , H01L27/115
CPC分类号： G11C16/0466 , G11C16/0483 , H01L23/535 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.
摘要翻译：提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。

45. 发明授权

US09059395B2 Resistive random access memory devices having variable resistance layers and related methods 有权
标题翻译：具有可变电阻层的电阻式随机存取存储器件及相关方法
公开(公告)号：US09059395B2
公开(公告)日：2015-06-16
申请号：US14090803
申请日：2013-11-26
申请人： Hyunsu Ju , Eunmi Kim , Yoocheol Shin , Min Kyu Yang , Jungdal Choi
发明人： Hyunsu Ju , Eunmi Kim , Yoocheol Shin , Min Kyu Yang , Jungdal Choi
IPC分类号： H01L29/02 , H01L45/00 , H01L27/24
CPC分类号： H01L45/08 , H01L27/2454 , H01L27/2481 , H01L45/1233 , H01L45/146
摘要： Resistive memory devices are provided having a gate stack including insulating layers and gates stacked on a substrate in a vertical direction, a channel penetrating the gate stack in the vertical direction to be electrically connected to the substrate, a gate insulating layer provided between the channel and the gates, and a variable resistance layer disposed along an extending direction of the channel. The gate stack may include an alcove formed by recessing the gate in a horizontal direction. The variable resistance layer may extend toward the alcove in the horizontal direction and be overlapped with at least one of the gates in the horizontal direction. Related methods are also provided.
摘要翻译：提供电阻式存储器件，其具有包括垂直方向上堆叠在基板上的绝缘层和栅极的栅极堆叠，在垂直方向上穿过栅极堆叠的沟道以电连接到衬底;栅极绝缘层，设置在沟道和栅极和沿通道的延伸方向设置的可变电阻层。栅极堆叠可以包括通过在水平方向上使栅极凹陷而形成的凹室。可变电阻层可以在水平方向上朝向凹室延伸，并且在水平方向上与至少一个栅极重叠。还提供了相关方法。

46. 发明授权

US08791520B2 Non-volatile memory devices having a floating gate cap between a floating gate and a gate insulating layer 有权
标题翻译：在浮置栅极和栅极绝缘层之间具有浮动栅极盖的非易失性存储器件
公开(公告)号：US08791520B2
公开(公告)日：2014-07-29
申请号：US12986553
申请日：2011-01-07
申请人： Jaeduk Lee , Albert Fayrushin , ByungKyu Cho , Jungdal Choi , Sunghoi Hur , Kwang Soo Seol , Dohyun Lee
发明人： Jaeduk Lee , Albert Fayrushin , ByungKyu Cho , Jungdal Choi , Sunghoi Hur , Kwang Soo Seol , Dohyun Lee
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/42336 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/42352 , H01L29/7881 , H01L29/792
摘要： Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.
摘要翻译：提供了非易失性存储器件及其形成方法。隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。控制栅极设置在栅极电介质图案上。

47. 发明申请

US20140140140A1 Vertical Nonvolatile Memory Devices and Methods of Operating Same 有权
标题翻译：垂直非易失性存储器件和操作方法相同
公开(公告)号：US20140140140A1
公开(公告)日：2014-05-22
申请号：US14164586
申请日：2014-01-27
申请人： Jaesung Sim , Jungdal Choi
发明人： Jaesung Sim , Jungdal Choi
IPC分类号： G11C16/34
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/14 , G11C16/3418
摘要： Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).
摘要翻译：集成电路存储器件包括多个垂直堆叠的非易失性存储器单元串，其中各个垂直布置的沟道区域在其中电耦合到下面的衬底。提供了一种控制电路，其被配置为在擦除时间间隔期间以从第一电压电平斜坡到较高的第二电压电平的擦除电压驱动垂直沟道区。擦除电压的上升促进了垂直堆叠的非易失性存储器单元的时间有效的擦除，从而降低了对无意编程接地和串选择晶体管（GST，SST）的敏感性。

48. 发明授权

US08625357B2 Local self-boosting method of flash memory device and program method using the same 有权
标题翻译：闪存器件的局部自增强方法及使用其的程序方法
公开(公告)号：US08625357B2
公开(公告)日：2014-01-07
申请号：US12917634
申请日：2010-11-02
申请人： ByungKyu Cho , Kwang Soo Seol , Sunghoi Hur , Jungdal Choi
发明人： ByungKyu Cho , Kwang Soo Seol , Sunghoi Hur , Jungdal Choi
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/3418
摘要： Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at both sides of a channel of a selected one of the memory cells. The channel of the selected memory cell is locally limited by the potential walls and boosted when a program voltage is applied to the selected memory cell.
摘要翻译：提供了一种闪存器件的局部自增强方法，其包括至少一个具有分别连接到字线的存储单元的串。局部自增强方法包括在串的通道处形成势阱，并在势阱处形成位于所选存储单元的通道两侧的电势壁。所选择的存储单元的通道在局部受到潜在的壁限制，并且当将程序电压施加到所选择的存储单元时升压。

49. 发明授权

US08446773B2 Memory system and programming method thereof 有权
标题翻译：存储器系统及其编程方法
公开(公告)号：US08446773B2
公开(公告)日：2013-05-21
申请号：US13272879
申请日：2011-10-13
申请人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
发明人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3454
摘要： Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage.
摘要翻译：提供了一种非易失性存储器系统及其编程方法。非易失性存储器系统的编程方法包括：参考要写入被配置为为所选存储器单元提供干扰的干扰单元的程序数据来调整所选择的存储器单元的编程验证电压，并根据调整后的程序验证电压。

50. 发明申请

US20120170375A1 Vertical Nonvolatile Memory Devices and Methods of Operating Same 有权
标题翻译：垂直非易失性存储器件和操作方法相同
公开(公告)号：US20120170375A1
公开(公告)日：2012-07-05
申请号：US13342361
申请日：2012-01-03
申请人： Jaesung Sim , Jungdal Choi
发明人： Jaesung Sim , Jungdal Choi
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/14 , G11C16/3418
摘要： Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).
摘要翻译：集成电路存储器件包括多个垂直堆叠的非易失性存储器单元串，其中各个垂直布置的沟道区域在其中电耦合到下面的衬底。提供了一种控制电路，其被配置为在擦除时间间隔期间以从第一电压电平斜坡到较高的第二电压电平的擦除电压驱动垂直沟道区。擦除电压的上升促进了垂直堆叠的非易失性存储器单元的时间有效的擦除，从而降低了对无意编程接地和串选择晶体管（GST，SST）的敏感性。

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