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41. 发明申请

US20070218607A1 Methods of Forming Single Crystalline Layers and Methods of Manufacturing Semiconductor Devices Having Such Layers 有权
标题翻译：形成单晶层的方法和制造具有这种层的半导体器件的方法
公开(公告)号：US20070218607A1
公开(公告)日：2007-09-20
申请号：US11751857
申请日：2007-05-22
申请人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee
发明人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee
IPC分类号： H01L21/84
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/02645 , H01L21/2026 , H01L21/8221 , H01L21/84 , H01L27/0688
摘要： In a method of forming a single crystalline semiconductor layer, an amorphous layer may be formed on a seed layer that includes a single crystalline material. The single crystalline layer may be formed from the amorphous layer by irradiating a laser beam onto the amorphous layer using the seed layer as a seed for a phase change of the amorphous layer. The laser beam may have an energy for melting the amorphous layer, and the laser beam may be irradiated onto the amorphous layer without generating a superimposedly irradiated region of the amorphous layer. The single crystalline layer may include a high density of large-sized grains without generating a protrusion thereon through a simple process so that a semiconductor device including the single crystalline layer may have a high degree of integration and improved electrical characteristics.
摘要翻译：在形成单晶半导体层的方法中，可以在包括单晶材料的籽晶层上形成非晶层。可以通过使用种子层作为非晶层相变的种子将激光束照射到非晶层上，由非晶层形成单晶层。激光束可以具有用于熔化非晶层的能量，并且可以将激光束照射到非晶层上而不产生非晶层的叠加照射的区域。单晶层可以包括高密度的大尺寸晶粒，而不通过简单的工艺在其上产生突起，使得包括单晶层的半导体器件可以具有高度集成度和改善的电特性。

42. 发明授权

US07700461B2 Methods of laterally forming single crystalline thin film regions from seed layers 失效
标题翻译：从种子层横向形成单晶薄膜区域的方法
公开(公告)号：US07700461B2
公开(公告)日：2010-04-20
申请号：US12061253
申请日：2008-04-02
申请人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Pil-Kyu Kang
发明人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Pil-Kyu Kang
IPC分类号： H01L21/20
CPC分类号： H01L21/8221 , H01L21/02381 , H01L21/02532 , H01L21/02667 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/1285 , H01L29/78675
摘要： In a method of manufacturing a semiconductor device, a string structure including a selection transistor and a memory cell on a substrate. An insulation layer pattern is formed on the substrate to cover the string structure. The insulation layer pattern includes at least one opening exposing a portion of the substrate adjacent to the selection transistor. A seed layer including a single-crystalline material is formed in the opening. An amorphous thin film including an amorphous material is formed on the insulation layer pattern and the seed layer. The amorphous thin film is transformed into a single-crystalline thin film, using the single-crystalline material in the seed layer as a seed during a phase transition of the amorphous thin film, to form a channel layer on the insulation layer pattern and the seed layer. Therefore, the semiconductor device including the channel layer having the single-crystalline thin film may be manufactured.
摘要翻译：在制造半导体器件的方法中，包括在衬底上的选择晶体管和存储单元的串联结构。在衬底上形成绝缘层图案以覆盖串结构。绝缘层图案包括暴露基板的与选择晶体管相邻的部分的至少一个开口。在开口中形成包括单晶材料的晶种层。在绝缘层图案和种子层上形成包含非晶材料的非晶态薄膜。在非晶薄膜的相变期间，将晶种层中的单晶材料作为种子，将非晶薄膜转变为单晶薄膜，以在绝缘层图案和种子上形成沟道层层。因此，可以制造包括具有单晶薄膜的沟道层的半导体器件。

43. 发明申请

US20080293224A1 METHOD OF FORMING A DIODE AND METHOD OF MANUFACTURING A PHASE-CHANGE MEMORY DEVICE USING THE SAME 审中-公开
标题翻译：二极管的制造方法和使用该二极管的相变存储器件的制造方法
公开(公告)号：US20080293224A1
公开(公告)日：2008-11-27
申请号：US12126120
申请日：2008-05-23
申请人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee
发明人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee
IPC分类号： H01L21/20
CPC分类号： H01L45/144 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： In a method of forming a diode, a first amorphous thin film doped with first impurities is formed on a single crystalline substrate. A second amorphous thin film doped with second impurities is formed on the first amorphous thin film. A laser beam having sufficient energy to melt both of the first and second amorphous thin films is irradiated on the first and second amorphous thin films to change crystal structures of the first and second amorphous thin films using the single crystalline substrate as a seed, so that first and second single crystalline thin films are sequentially formed on the single crystalline substrate.
摘要翻译：在形成二极管的方法中，在单晶衬底上形成掺杂有第一杂质的第一非晶薄膜。掺杂有第二杂质的第二非晶薄膜形成在第一非晶薄膜上。将具有足够的能量来熔化第一和第二非晶薄膜的激光束照射在第一和第二非晶薄膜上，以使用单晶基板作为种子来改变第一和第二非晶薄膜的晶体结构，从而使得第一和第二单晶薄膜依次形成在单晶衬底上。

44. 发明申请

US20080179665A1 Semiconductor Memory Devices and Methods of Forming the Same 审中-公开
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20080179665A1
公开(公告)日：2008-07-31
申请号：US12019046
申请日：2008-01-24
申请人： Jong-Wook Lee , Yong-Hoon Son , Si-Young Choi
发明人： Jong-Wook Lee , Yong-Hoon Son , Si-Young Choi
IPC分类号： H01L29/78
CPC分类号： H01L29/7841 , H01L21/268 , H01L27/0207 , H01L27/108 , H01L27/10802
摘要： A memory cell transistor includes a semiconductor substrate having a first impurity region of first conductivity type (e.g., N-type) therein. A U-shaped semiconductor layer having a second impurity region of first conductivity type therein is provided on the first impurity region. A gate insulating layer is provided, which lines a bottom and an inner sidewall of the U-shaped semiconductor layer. A gate electrode is provided on the gate insulating layer. The gate electrode is surrounded by the inner sidewall of the U-shaped semiconductor layer. A word line is provided, which is electrically coupled to the gate electrode, and a bit line is provided, which is electrically coupled to the second impurity region.
摘要翻译：存储单元晶体管包括其中具有第一导电类型的第一杂质区（例如N型）的半导体衬底。具有第一导电类型的第二杂质区的U形半导体层设置在第一杂质区上。提供了栅极绝缘层，其对U形半导体层的底部和内侧壁进行排列。栅电极设置在栅极绝缘层上。栅电极被U形半导体层的内侧壁包围。提供字线，其电耦合到栅电极，并且提供与第二杂质区电耦合的位线。

45. 发明授权

US08592873B2 Semiconductor memory devices and methods of forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US08592873B2
公开(公告)日：2013-11-26
申请号：US13167858
申请日：2011-06-24
申请人： Jung Ho Kim , Daehyun Jang , Myoungbum Lee , Kihyun Hwang , Sangryol Yang , Yong-Hoon Son , Ju-Eun Kim , Sunghae Lee , Dongwoo Kim , JinGyun Kim
发明人： Jung Ho Kim , Daehyun Jang , Myoungbum Lee , Kihyun Hwang , Sangryol Yang , Yong-Hoon Son , Ju-Eun Kim , Sunghae Lee , Dongwoo Kim , JinGyun Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/11582 , H01L21/02675 , H01L21/30604 , H01L21/324 , H01L27/11551 , H01L27/11578 , H01L29/7926
摘要： Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region.
摘要翻译：可以提供半导体器件及其形成方法。半导体器件可以包括在衬底上重复并交替堆叠的栅极图案和绝缘图案。半导体器件还可以包括穿透栅极图案和绝缘图案的穿透区域。半导体器件还可以包括从衬底延伸穿过区域的沟道结构。通道结构可以包括具有第一形状的第一通道图案。第一沟道图案可以包括贯通区域的一部分的侧壁上的第一半导体区域和分割第一半导体区域的掩埋图案。通道结构还可以包括具有第二形状的第二通道图案。第二沟道图案可以包括通孔区域中的第二半导体区域。第二半导体区域的晶粒尺寸可以大于第一半导体区域的晶粒尺寸。

46. 发明授权

US08482049B2 Semiconductor devices and methods for fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08482049B2
公开(公告)日：2013-07-09
申请号：US12968389
申请日：2010-12-15
申请人： Yong-Hoon Son , Seungjae Baik , Jaehun Jeong , Kihun Hwang
发明人： Yong-Hoon Son , Seungjae Baik , Jaehun Jeong , Kihun Hwang
IPC分类号： H01L29/76
CPC分类号： G11C16/0483 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/66666 , H01L29/7827 , H01L29/7926
摘要： In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.
摘要翻译：在半导体器件和制造方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。多个层间电介质层位于基板上。提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间电介质层之间。半导体材料的垂直沟道位于衬底上并沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案。垂直通道具有外侧壁，外侧壁具有多个通道凹槽，每个通道凹槽对应于多个栅极图案的栅极图案。垂直通道具有内侧壁。在每个栅极图案和垂直沟道之间的凹槽中存在信息存储层，其将栅极图案与垂直沟道绝缘。

47. 发明授权

US08455316B2 Method of manufacturing vertical semiconductor device 有权
标题翻译：垂直半导体器件制造方法
公开(公告)号：US08455316B2
公开(公告)日：2013-06-04
申请号：US13325189
申请日：2011-12-14
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , B82Y10/00 , H01L21/823487 , H01L27/10876 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.
摘要翻译：垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分，所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层，所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。

48. 发明授权

US08450176B2 Methods of manufacturing rewriteable three-dimensional semiconductor memory devices 有权
标题翻译：制造可重写三维半导体存储器件的方法
公开(公告)号：US08450176B2
公开(公告)日：2013-05-28
申请号：US12968595
申请日：2010-12-15
申请人： Yong-Hoon Son , Kihyun Hwang , Seungjae Baik
发明人： Yong-Hoon Son , Kihyun Hwang , Seungjae Baik
IPC分类号： H01L21/336
CPC分类号： H01L21/28 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.
摘要翻译：形成非易失性存储器件的方法包括在衬底上形成垂直堆叠的非易失性存储单元。这通过在垂直硅有源层的第一侧壁上形成间隔开的栅电极的垂直堆叠来完成，并且处理垂直硅有源层的第二侧壁以便减少有源层内的晶体缺陷和/或减少界面其中的陷阱密度。该处理可以包括用氧化物质暴露第二侧壁，该氧化物质将第二侧壁的表面转化为二氧化硅钝化层。也可以直接在二氧化硅钝化层上形成掩埋绝缘图案。

49. 发明授权

US08445317B2 Methods of fabricating semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08445317B2
公开(公告)日：2013-05-21
申请号：US13030454
申请日：2011-02-18
申请人： Jin Ha Jeong , Jung-Ho Kim , Kihyun Hwang , Yong-Hoon Son
发明人： Jin Ha Jeong , Jung-Ho Kim , Kihyun Hwang , Yong-Hoon Son
IPC分类号： H01L21/84
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/42352 , H01L29/4236 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/7926
摘要： Methods for fabricating a semiconductor device are provided. In the methods, first material layers and second material layers may be alternatingly and repeatedly stacked on a substrate. An opening penetrating the first material layers and the second material layers may be formed. A semiconductor solution may be formed in the opening by using a spin-on process.
摘要翻译：提供了制造半导体器件的方法。在这些方法中，第一材料层和第二材料层可以交替地和重复堆叠在基底上。可以形成贯穿第一材料层和第二材料层的开口。可以通过使用旋涂工艺在开口中形成半导体溶液。

50. 发明申请

US20130115761A1 Methods of Forming a Semiconductor Device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20130115761A1
公开(公告)日：2013-05-09
申请号：US13724632
申请日：2012-12-21
申请人： Jung Ho Kim , Sunghae Lee , Hanvit Yang , Dongwoo Kim , Chaeho Kim , Daehyun Jang , Ju-Eun Kim , Yong-Hoon Son , Sangryol Yang , Myoungbum Lee , Kihyun Hwang
发明人： Jung Ho Kim , Sunghae Lee , Hanvit Yang , Dongwoo Kim , Chaeho Kim , Daehyun Jang , Ju-Eun Kim , Yong-Hoon Son , Sangryol Yang , Myoungbum Lee , Kihyun Hwang
IPC分类号： H01L21/04
CPC分类号： H01L21/04 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.
摘要翻译：提供了形成半导体器件的方法。所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层，以及形成穿透第一层和第二层的开口。所述方法还可以包括在开口中形成第一半导体图案。所述方法还可以包括在第一半导体图案上形成绝缘图案。所述方法还可以包括在绝缘图案上形成第二半导体图案。所述方法还可以包括在第一半导体图案中提供掺杂剂。此外，所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。

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