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1. 发明申请

US20150333084A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：三维半导体存储器件及其形成方法
公开(公告)号：US20150333084A1
公开(公告)日：2015-11-19
申请号：US14810845
申请日：2015-07-28
申请人： Yong-Hoon Son , Jung Ho Kim , Seungjae Baik , Myoungbum Lee , Kihyun Hwang
发明人： Yong-Hoon Son , Jung Ho Kim , Seungjae Baik , Myoungbum Lee , Kihyun Hwang
IPC分类号： H01L27/115
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.
摘要翻译：非易失性存储器件包括在衬底上的一串非易失性存储器单元。这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。在衬底中提供连接掺杂半导体区域。该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

2. 发明授权

US08450176B2 Methods of manufacturing rewriteable three-dimensional semiconductor memory devices 有权
标题翻译：制造可重写三维半导体存储器件的方法
公开(公告)号：US08450176B2
公开(公告)日：2013-05-28
申请号：US12968595
申请日：2010-12-15
申请人： Yong-Hoon Son , Kihyun Hwang , Seungjae Baik
发明人： Yong-Hoon Son , Kihyun Hwang , Seungjae Baik
IPC分类号： H01L21/336
CPC分类号： H01L21/28 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.
摘要翻译：形成非易失性存储器件的方法包括在衬底上形成垂直堆叠的非易失性存储单元。这通过在垂直硅有源层的第一侧壁上形成间隔开的栅电极的垂直堆叠来完成，并且处理垂直硅有源层的第二侧壁以便减少有源层内的晶体缺陷和/或减少界面其中的陷阱密度。该处理可以包括用氧化物质暴露第二侧壁，该氧化物质将第二侧壁的表面转化为二氧化硅钝化层。也可以直接在二氧化硅钝化层上形成掩埋绝缘图案。

3. 发明申请

US20110248327A1 Three-Dimensional Semiconductor Memory Devices and Methods of Forming the Same 审中-公开
标题翻译：三维半导体存储器件及其形成方法
公开(公告)号：US20110248327A1
公开(公告)日：2011-10-13
申请号：US13039043
申请日：2011-03-02
申请人： Yong-Hoon Son , Myoungbum Lee , Kihyun Hwang , Seungjae Baik , Jung Ho Kim
发明人： Yong-Hoon Son , Myoungbum Lee , Kihyun Hwang , Seungjae Baik , Jung Ho Kim
IPC分类号： H01L27/115
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.
摘要翻译：非易失性存储器件包括在衬底上的一串非易失性存储器单元。这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。在衬底中提供连接掺杂半导体区域。该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

4. 发明申请

US20110143524A1 Methods of Manufacturing Rewriteable Three-Dimensional Semiconductor Memory Devices 有权
标题翻译：制造可重写三维半导体存储器件的方法
公开(公告)号：US20110143524A1
公开(公告)日：2011-06-16
申请号：US12968595
申请日：2010-12-15
申请人： Yong-Hoon Son , Kihyun Hwang , Seungjae Baik
发明人： Yong-Hoon Son , Kihyun Hwang , Seungjae Baik
IPC分类号： H01L21/28 , H01L21/20
CPC分类号： H01L21/28 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.
摘要翻译：形成非易失性存储器件的方法包括在衬底上形成垂直堆叠的非易失性存储单元。这通过在垂直硅有源层的第一侧壁上形成间隔开的栅电极的垂直堆叠来完成，并且处理垂直硅有源层的第二侧壁以便减少有源层内的晶体缺陷和/或减少界面其中的陷阱密度。该处理可以包括用氧化物质暴露第二侧壁，该氧化物质将第二侧壁的表面转化为二氧化硅钝化层。也可以直接在二氧化硅钝化层上形成掩埋绝缘图案。

5. 发明授权

US09356033B2 Three-dimensional semiconductor memory devices and methods of forming the same 有权
标题翻译：三维半导体存储器件及其形成方法
公开(公告)号：US09356033B2
公开(公告)日：2016-05-31
申请号：US14810845
申请日：2015-07-28
申请人： Yong-Hoon Son , Jung Ho Kim , Seungjae Baik , Myoungbum Lee , Kihyun Hwang
发明人： Yong-Hoon Son , Jung Ho Kim , Seungjae Baik , Myoungbum Lee , Kihyun Hwang
IPC分类号： H01L29/66 , H01L29/78 , H01L27/115
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.
摘要翻译：非易失性存储器件包括在衬底上的一串非易失性存储器单元。这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。在衬底中提供连接掺杂半导体区域。该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

6. 发明授权

US08482049B2 Semiconductor devices and methods for fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08482049B2
公开(公告)日：2013-07-09
申请号：US12968389
申请日：2010-12-15
申请人： Yong-Hoon Son , Seungjae Baik , Jaehun Jeong , Kihun Hwang
发明人： Yong-Hoon Son , Seungjae Baik , Jaehun Jeong , Kihun Hwang
IPC分类号： H01L29/76
CPC分类号： G11C16/0483 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/66666 , H01L29/7827 , H01L29/7926
摘要： In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.
摘要翻译：在半导体器件和制造方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。多个层间电介质层位于基板上。提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间电介质层之间。半导体材料的垂直沟道位于衬底上并沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案。垂直通道具有外侧壁，外侧壁具有多个通道凹槽，每个通道凹槽对应于多个栅极图案的栅极图案。垂直通道具有内侧壁。在每个栅极图案和垂直沟道之间的凹槽中存在信息存储层，其将栅极图案与垂直沟道绝缘。

7. 发明申请

US20110147824A1 SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147824A1
公开(公告)日：2011-06-23
申请号：US12968389
申请日：2010-12-15
申请人： Yong-Hoon Son , Seungjae Baik , Jaehun Jeong , Kihun Hwang
发明人： Yong-Hoon Son , Seungjae Baik , Jaehun Jeong , Kihun Hwang
IPC分类号： H01L29/792
CPC分类号： G11C16/0483 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/66666 , H01L29/7827 , H01L29/7926
摘要： In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.
摘要翻译：在半导体器件和制造方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。多个层间电介质层位于基板上。提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间电介质层之间。半导体材料的垂直沟道位于衬底上并沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案。垂直通道具有外侧壁，外侧壁具有多个通道凹槽，每个通道凹槽对应于多个栅极图案的栅极图案。垂直通道具有内侧壁。在每个栅极图案和垂直沟道之间的凹槽中存在信息存储层，其将栅极图案与垂直沟道绝缘。

8. 发明授权

US08507918B2 Multilayer semiconductor devices with channel patterns having a graded grain structure 有权
标题翻译：具有沟道图案的具有渐变晶粒结构的多层半导体器件
公开(公告)号：US08507918B2
公开(公告)日：2013-08-13
申请号：US13018833
申请日：2011-02-01
申请人： Yong-Hoon Son , Myoungbum Lee , Kihyun Hwang
发明人： Yong-Hoon Son , Myoungbum Lee , Kihyun Hwang
IPC分类号： H01L29/04
CPC分类号： H01L27/11582
摘要： Memory devices include a stack of interleaved conductive patterns and insulating patterns disposed on a substrate. A semiconductor pattern passes through the stack of conductive patterns and insulating patterns to contact the substrate, the semiconductor pattern having a graded grain size distribution wherein a mean grain size in a first portion of the semiconductor pattern proximate the substrate is less than a mean grain size in a second portion of the semiconductor pattern further removed from the substrate. The graded grain size distribution may be achieved, for example, by partial laser annealing.
摘要翻译：存储器件包括布置在衬底上的交错导电图案和绝缘图案的堆叠。半导体图形通过导体图案和绝缘图案堆叠以接触衬底，半导体图案具有渐变的晶粒尺寸分布，其中半导体图案的靠近衬底的第一部分中的平均晶粒尺寸小于平均晶粒尺寸在从衬底进一步去除的半导体图案的第二部分中。分级粒度分布可以通过例如部分激光退火来实现。

9. 发明申请

US20110207303A1 Methods of Fabricating Semiconductor Devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110207303A1
公开(公告)日：2011-08-25
申请号：US13030454
申请日：2011-02-18
申请人： Jin Ha Jeong , Jung Ho Kim , Kihyun Hwang , Yong-Hoon Son
发明人： Jin Ha Jeong , Jung Ho Kim , Kihyun Hwang , Yong-Hoon Son
IPC分类号： H01L21/368
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/42352 , H01L29/4236 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/7926
摘要： Methods for fabricating a semiconductor device are provided. In the methods, first material layers and second material layers may be alternatingly and repeatedly stacked on a substrate. An opening penetrating the first material layers and the second material layers may be formed. A semiconductor solution may be formed in the opening by using a spin-on process.
摘要翻译：提供了制造半导体器件的方法。在这些方法中，第一材料层和第二材料层可以交替地和重复堆叠在基底上。可以形成贯穿第一材料层和第二材料层的开口。可以通过使用旋涂工艺在开口中形成半导体溶液。

10. 发明授权

US08592873B2 Semiconductor memory devices and methods of forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US08592873B2
公开(公告)日：2013-11-26
申请号：US13167858
申请日：2011-06-24
申请人： Jung Ho Kim , Daehyun Jang , Myoungbum Lee , Kihyun Hwang , Sangryol Yang , Yong-Hoon Son , Ju-Eun Kim , Sunghae Lee , Dongwoo Kim , JinGyun Kim
发明人： Jung Ho Kim , Daehyun Jang , Myoungbum Lee , Kihyun Hwang , Sangryol Yang , Yong-Hoon Son , Ju-Eun Kim , Sunghae Lee , Dongwoo Kim , JinGyun Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/11582 , H01L21/02675 , H01L21/30604 , H01L21/324 , H01L27/11551 , H01L27/11578 , H01L29/7926
摘要： Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region.
摘要翻译：可以提供半导体器件及其形成方法。半导体器件可以包括在衬底上重复并交替堆叠的栅极图案和绝缘图案。半导体器件还可以包括穿透栅极图案和绝缘图案的穿透区域。半导体器件还可以包括从衬底延伸穿过区域的沟道结构。通道结构可以包括具有第一形状的第一通道图案。第一沟道图案可以包括贯通区域的一部分的侧壁上的第一半导体区域和分割第一半导体区域的掩埋图案。通道结构还可以包括具有第二形状的第二通道图案。第二沟道图案可以包括通孔区域中的第二半导体区域。第二半导体区域的晶粒尺寸可以大于第一半导体区域的晶粒尺寸。

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