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41. 发明授权

US06274421B1 Method of making metal gate sub-micron MOS transistor 失效
标题翻译：制造金属栅极亚微米MOS晶体管的方法
公开(公告)号：US06274421B1
公开(公告)日：2001-08-14
申请号：US09004991
申请日：1998-01-09
申请人： Sheng Teng Hsu , David R. Evans , Tue Nguyen
发明人： Sheng Teng Hsu , David R. Evans , Tue Nguyen
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/28088 , H01L21/28097 , H01L21/76895 , H01L21/76897 , H01L21/82385 , H01L29/42376 , H01L29/4966 , H01L29/4975 , H01L29/66545
摘要： A MOS transistor is formed on a single crystal silicon substrate doped to form a conductive layer of a first type, and includes: an active region formed on said substrate; a source region and a drain region located in said active region, doped to form conductive channels of a second type; a metal gate region located in said active region between said source region and said drain region, wherein said metal gate has a width of less than one micron; a gate oxide region located over said gate region; an oxide region located over the structure; and a source electrode, a gate electrode and a drain electrode, each connected to their respective regions, and each formed of a combination of a contact metal and an electrode metal. An alternate embodiment includes a pair of MOS transistors which have an interconnect between their gate electrodes and the drain electrode of one transistor and the drain electrode of the other transistor.
摘要翻译： MOS晶体管形成在掺杂以形成第一类型的导电层的单晶硅衬底上，并且包括：形成在所述衬底上的有源区; 位于所述有源区中的源极区和漏极区，被掺杂以形成第二类型的导电沟道; 位于所述源极区域和所述漏极区域之间的所述有源区域中的金属栅极区域，其中所述金属栅极具有小于1微米的宽度; 位于所述栅极区域上方的栅极氧化物区域; 位于结构上方的氧化物区域; 以及源电极，栅电极和漏电极，各自连接到它们各自的区域，并且各自由接触金属和电极金属的组合形成。替代实施例包括一对MOS晶体管，它们在其栅电极和一个晶体管的漏电极和另一晶体管的漏电极之间具有互连。

42. 发明授权

US5907762A Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing 失效
标题翻译：使用化学机械抛光制造单晶体铁电存储器单元的方法
公开(公告)号：US5907762A
公开(公告)日：1999-05-25
申请号：US984789
申请日：1997-12-04
申请人： David R. Evans , Sheng Teng Hsu , Jong Jan Lee
发明人： David R. Evans , Sheng Teng Hsu , Jong Jan Lee
IPC分类号： H01L21/318 , H01L21/304 , H01L21/336 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L29/78 , H01L21/00
CPC分类号： H01L29/66477 , H01L29/78391
摘要： A method of constructing a single-transistor ferroelectric memory (FEM) cell includes: preparing a silicon substrate for construction of a FEM gate unit; forming gate, source and drain regions on the silicon substrate; forming a nitride layer over the structure to a predetermined thickness equal to a specified thickness for a bottom electrode of the FEM gate unit; forming a first insulating layer over the structure; chemically-mechanically polishing the first insulating layer such that the top surface thereof is even with the top of the nitride layer; forming the bottom electrode for the FEM cell; and chemically-mechanically polishing the bottom electrode such that the top surface thereof is even with the top surface of the first insulating layer. Additional layers are formed and polished, depending on the specific final configuration of the FEM cell.
摘要翻译：构成单晶体管铁电存储器（FEM）单元的方法包括：制备用于构造有限元栅极单元的硅衬底; 在硅衬底上形成栅极，源极和漏极区域; 在所述结构上形成等于所述FEM栅极单元的底部电极的指定厚度的预定厚度的氮化物层; 在所述结构上形成第一绝缘层; 化学机械抛光第一绝缘层，使得其顶表面与氮化物层的顶部均匀; 形成有限元电池的底电极; 并对底部电极进行化学机械抛光，使得其顶表面与第一绝缘层的顶表面均匀。根据FEM单元的具体最终配置，形成和抛光附加层。

43. 发明授权

US08264081B2 Multilayered barrier metal thin-films 有权
标题翻译：多层阻隔金属薄膜
公开(公告)号：US08264081B2
公开(公告)日：2012-09-11
申请号：US11311546
申请日：2005-12-19
申请人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28562 , H01L21/76841 , H01L2221/1078
摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.
摘要翻译：通过原子层化学气相沉积（ALCVD）将多层阻挡金属薄膜沉积在衬底上。多层膜可以包括单个化学物质的几个不同层，或者各个不同的或交替的化学物质的几个层。在优选实施例中，多层阻挡薄膜包括在衬底上的氮化钽层，其上沉积有氮化钛层。整个多层膜的厚度可以是大约50埃。当与通过常规化学气相沉积（CVD）沉积的膜相比时，该膜具有优异的膜特性，例如抗扩散能力，低电阻率，高密度和台阶覆盖。本发明的多层阻挡金属薄膜具有改善的粘合特性，特别适用于其上的铜膜的金属化。

44. 发明申请

US20090032817A1 Back-To-Back Metal/Semiconductor/Metal (MSM) Schottky Diode 有权
标题翻译：背对背金属/半导体/金属（MSM）肖特基二极管
公开(公告)号：US20090032817A1
公开(公告)日：2009-02-05
申请号：US12234663
申请日：2008-09-21
申请人： Tingkai Li , Sheng Teng Hsu , David R. Evans
发明人： Tingkai Li , Sheng Teng Hsu , David R. Evans
IPC分类号： H01L29/04 , H01L21/329
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
摘要翻译：提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。通常，响应于Si厚度的增加，阈值和击穿电压都增加。关于开/关电流比，存在最佳厚度。该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

45. 发明授权

US07364665B2 Selective etching processes of SiO2 , Ti and In2 O3 thin films for FeRAM device applications 失效
标题翻译：用于FeRAM器件应用的SiO2，Ti和In2 O3薄膜的选择性蚀刻工艺
公开(公告)号：US07364665B2
公开(公告)日：2008-04-29
申请号：US10970885
申请日：2004-10-21
申请人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L29/6684 , C23F4/00 , H01L21/28291 , H01L21/31116 , H01L21/32136
摘要： A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.
摘要翻译：选择性地蚀刻由SiO 2，In 2 O 3 N 3和Ti构成的三层结构的方法包括蚀刻SiO _{2 ，在钛层上停止，使用C 3 3 F 8 N在约10sccm至30sccm之间; 在约20sccm至40sccm的范围内的氩气，使用在约1000瓦特至3000瓦特之间的范围内的RF源和在约400瓦特至800瓦特范围内的RF偏压，约2mtorr至6mtorr; 并且使用在约10sccm至50sccm之间的范围内的BCl蚀刻钛，停止在In 2 N 3 O 3层处; 在约40sccm至80sccm的范围内的氯，在约200瓦特至200瓦特之间的RF偏压下在约200瓦特至500瓦特之间的范围内的T cp < 在约4mtorr至8mtorr的范围内的压力。}

46. 发明授权

US07361574B1 Single-crystal silicon-on-glass from film transfer 有权
标题翻译：单晶硅玻璃从膜转移
公开(公告)号：US07361574B1
公开(公告)日：2008-04-22
申请号：US11601173
申请日：2006-11-17
申请人： Jer-Shen Maa , David R. Evans , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , David R. Evans , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/30 , H01L21/461
CPC分类号： H01L21/76251 , H01L21/84 , Y10S438/926 , Y10S438/933
摘要： A method is provided for transferring a single-crystal silicon (Si) film to a glass substrate. The method deposits a germanium (Ge)-containing material overlying a Si wafer, forming a sacrificial Ge-containing film. A single-crystal Si film is formed overlying the sacrificial Ge-containing film. The Si film surface is bonded to a transparent substrate, forming a bonded substrate. The bonded substrate is immersed in a Ge etching solution to remove the sacrificial Ge-containing film, which separates the transparent substrate from the Si wafer. The result is a transparent substrate with an overlying single crystal Si film. Optionally, channels can be formed to distribute the Ge etching solution, and promote the removal of the Ge-containing film.
摘要翻译：提供了将单晶硅（Si）膜转印到玻璃基板上的方法。该方法沉积覆盖Si晶片的含锗（Ge）的材料，形成牺牲含Ge膜。形成覆盖牺牲的含Ge膜的单晶Si膜。将Si膜表面粘合到透明基板上，形成键合衬底。将键合衬底浸入Ge蚀刻溶液中以除去将透明衬底与Si晶片分离的牺牲Ge含量膜。结果是具有上覆单晶Si膜的透明衬底。可选地，可以形成通道以分布Ge蚀刻溶液，并促进除去含Ge膜。

47. 发明授权

US07241670B2 Method to form relaxed SiGe layer with high Ge content using co-implantation of silicon with boron or helium and hydrogen 失效
标题翻译：使用硅与硼或氦和氢的共同注入形成具有高Ge含量的弛豫SiGe层的方法
公开(公告)号：US07241670B2
公开(公告)日：2007-07-10
申请号：US10936400
申请日：2004-09-07
申请人： Douglas J. Tweet , David R. Evans , Sheng Teng Hsu , Jer-Shen Maa
发明人： Douglas J. Tweet , David R. Evans , Sheng Teng Hsu , Jer-Shen Maa
IPC分类号： H01L21/26 , H01L21/42
CPC分类号： H01L21/02694 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L29/1054 , Y10S438/933
摘要： A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions selected from the group of ions consisting of boron and helium, and which further includes implanting H+ ions; annealing to relax the strained SiGe layer, thereby forming a first relaxed SiGe layer; and completing the semiconductor device.
摘要翻译：在半导体器件中形成具有高锗含量的弛豫SiGe层的方法包括制备硅衬底; 沉积应变SiGe层; 将离子注入到应变SiGe层中，其中离子包括选自由硼和氦构成的离子组的硅离子和离子，并且还包括注入H +离子; 退火以使应变SiGe层松弛，从而形成第一弛豫SiGe层; 并完成半导体器件。

48. 发明授权

US07192866B2 Source alternating MOCVD processes to deposit tungsten nitride thin films as barrier layers for MOCVD copper interconnects 失效
标题翻译：源交替MOCVD工艺沉积氮化钨薄膜作为MOCVD铜互连的阻挡层
公开(公告)号：US07192866B2
公开(公告)日：2007-03-20
申请号：US10326712
申请日：2002-12-19
申请人： Wei Pan , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/28556 , H01L2221/1078
摘要： An alternating source MOCVD process is provided for depositing tungsten nitride thin films for use as barrier layers for copper interconnects. Alternating the tungsten precursor produces fine crystal grain films, or possibly amorphous films. The nitrogen source may also be alternated to form WN/W alternating layer films, as tungsten is deposited during periods where the nitrogen source is removed.
摘要翻译：提供了用于沉积用作铜互连的阻挡层的氮化钨薄膜的交替源MOCVD工艺。交替钨前体产生细晶粒膜或可能的非晶膜。氮源也可以交替形成WN / W交替层膜，因为在氮源被去除的时期期间钨被沉积。

49. 发明授权

US07015138B2 Multi-layered barrier metal thin films for Cu interconnect by ALCVD 有权
公开(公告)号：US07015138B2
公开(公告)日：2006-03-21
申请号：US09819296
申请日：2001-03-27
申请人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/44
CPC分类号： H01L21/28562 , H01L21/76841 , H01L2221/1078
摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

50. 发明授权

US06939724B2 Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer 有权
公开(公告)号：US06939724B2
公开(公告)日：2005-09-06
申请号：US10640770
申请日：2003-08-13
申请人： Wei-Wei Zhuang , Tingkai Li , David R. Evans , Sheng Teng Hsu , Wei Pan
发明人： Wei-Wei Zhuang , Tingkai Li , David R. Evans , Sheng Teng Hsu , Wei Pan
IPC分类号： H01L27/04 , H01L21/20 , H01L21/822 , H01L45/00 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

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