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41. 发明授权

US08114768B2 Electromigration resistant via-to-line interconnect 有权
标题翻译：防电互连线路互连
公开(公告)号：US08114768B2
公开(公告)日：2012-02-14
申请号：US12344838
申请日：2008-12-29
申请人： Baozhen Li , Paul S. McLaughlin , Timothy D. Sullivan
发明人： Baozhen Li , Paul S. McLaughlin , Timothy D. Sullivan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.
摘要翻译：在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触重叠变化。

42. 发明申请

US20110115508A1 DETERMINING CRITICAL CURRENT DENSITY FOR INTERCONNECT 失效
标题翻译：确定互连的关键电流密度
公开(公告)号：US20110115508A1
公开(公告)日：2011-05-19
申请号：US12620955
申请日：2009-11-18
申请人： Chad M. Burke , Cathryn J. Christiansen , Baozhen Li
发明人： Chad M. Burke , Cathryn J. Christiansen , Baozhen Li
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： Solutions for determining a critical current density of a line are disclosed. In one embodiment a method of determining a critical current density in a line includes: applying a temperature condition to each of a plurality of samples including the line; calculating a cross-sectional area of the line for each of the plurality samples using data about an electrical resistance of the line over each of the temperature conditions; measuring an electrical current reading through the line for each of the plurality of samples; determining a current density through the line for each of the plurality of samples by dividing each electrical current reading by each corresponding cross-sectional area; determining an electromigration (EM) failure time for each of the plurality of samples; and determining the critical current density of the line using the current density and the plurality of EM failure times.
摘要翻译：公开了用于确定线的临界电流密度的解决方案。在一个实施例中，确定线中的临界电流密度的方法包括：对包括线的多个样本中的每一个施加温度条件; 使用关于在每个温度条件下的线的电阻的数据来计算多个样本中的每个样本的线的横截面面积; 测量所述多个样本中的每一个的所述线的电流读数; 通过将每个电流读数除以每个对应的横截面积来确定通过所述多个样品中的每一个的所述线的电流密度; 确定所述多个样本中的每一个的电迁移（EM）故障时间; 以及使用电流密度和多个EM故障时间确定线路的临界电流密度。

43. 发明授权

US08726201B2 Method and system to predict a number of electromigration critical elements 失效
标题翻译：预测一些电迁移关键要素的方法和系统
公开(公告)号：US08726201B2
公开(公告)日：2014-05-13
申请号：US12780138
申请日：2010-05-14
申请人： Jeanne P. Bickford , Peter A. Habitz , Baozhen Li , Paul S. McLaughlin , Dileep N. Netrabile
发明人： Jeanne P. Bickford , Peter A. Habitz , Baozhen Li , Paul S. McLaughlin , Dileep N. Netrabile
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/10
摘要： A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.
摘要翻译：一种用于预测半导体产品中多个电迁移关键元件的方法和系统。该方法包括使用运行在计算机设备上的设计工具并且基于增加的可靠性温度和增加的预期电流中的至少一个来确定电路设计库中的多个库元件的关键要素因子。该方法还包括：（i）产品中包含的多个库元素中的相应数量的数量，以及（ii）关键要素因素来确定产品中的关键元素的数量。

44. 发明授权

US07173338B2 Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing 有权
标题翻译：局部金属沉淀形成的抑制和半导体加工中相应的金属化消耗
公开(公告)号：US07173338B2
公开(公告)日：2007-02-06
申请号：US10708486
申请日：2004-03-06
申请人： Jonathan D. Chapple-Sokol , Terence B. Hook , Baozhen Li , Thomas L. McDevitt , Christopher A. Ponsolle , Bette B. Reuter , Timothy D. Sullivan , Jeffrey S. Zimmerman
发明人： Jonathan D. Chapple-Sokol , Terence B. Hook , Baozhen Li , Thomas L. McDevitt , Christopher A. Ponsolle , Bette B. Reuter , Timothy D. Sullivan , Jeffrey S. Zimmerman
IPC分类号： H01L23/48
CPC分类号： H01L21/7684 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.
摘要翻译：用于抑制半导体加工中的局部金属沉淀形成（LMPF）的方法和结构。对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。可以在金属线周围形成监测斜坡端子并与金属线电断开。通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

45. 发明授权

US07064409B2 Structure and programming of laser fuse 有权
标题翻译：激光熔丝的结构和编程
公开(公告)号：US07064409B2
公开(公告)日：2006-06-20
申请号：US10605885
申请日：2003-11-04
申请人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
发明人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L23/525 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.
摘要翻译：用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的第一介电层。熔丝连接在第一电介质层的顶部。熔断体将两个通孔电连接并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。两个台面位于熔丝链上方，直接穿过两个通孔。两个台面各自包括第三自钝化导电材料。激光熔丝通过将激光束引导到熔丝链来编程。控制激光束，使得响应于激光束对熔丝链的影响，熔丝链的电阻改变，但熔丝链不会被吹掉。这种电阻变化被检测并转换成数字信号。

46. 发明授权

US5256272A Electrochemical sensor for determining the level of a certain metal in metals and alloys 失效
标题翻译：用于确定金属和合金中某种金属的水平的电化学传感器
公开(公告)号：US5256272A
公开(公告)日：1993-10-26
申请号：US848872
申请日：1992-03-10
申请人： Charles B. Alcock , Baozhen Li
发明人： Charles B. Alcock , Baozhen Li
IPC分类号： G01N27/403 , G01N27/416 , G01N27/26
CPC分类号： G01N27/4114
摘要： An electrochemical sensor for determination of the activity of a certain metal in a metal or alloy being tested comprises a solid electrolyte consisting of a solid solution of strontium fluoride and lanthanum fluoride to which is added a dispersed phase of a fluoride of such certain metal, a reference electrode of known concentration of such certain metal placed in contact with one face of the electrolyte, an opposite face of the solid electrolyte being in contact with the metal or alloy being tested, and a device for measuring the chemical potential difference between the reference electrode and the metal or alloy being tested.
摘要翻译：用于测定被测金属或合金中某种金属的活性的电化学传感器包括由氟化锶和氟化镧的固溶体组成的固体电解质，其中加入这种某种金属的氟化物的分散相，已知浓度的已知浓度的参比电极放置成与电解质的一个面接触，固体电解质的正面与被测试的金属或合金接触，以及用于测量参比电极之间的化学势差的装置和正在测试的金属或合金。

47. 发明申请

US20090302476A1 Structures and Methods to Enhance CU Interconnect Electromigration (EM) Performance 有权
标题翻译：增强CU互连电迁移（EM）性能的结构和方法
公开(公告)号：US20090302476A1
公开(公告)日：2009-12-10
申请号：US12132806
申请日：2008-06-04
申请人： Baozhen Li
发明人： Baozhen Li
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76834 , H01L21/76832 , H01L21/76849 , Y10S438/927
摘要： The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in interconnects. A method includes forming an interconnect, forming a cap on the interconnect, and forming a plurality of holes in the cap to improve electromigration performance of the interconnect.
摘要翻译：本发明一般涉及半导体器件，更具体地涉及用于增强互连中的电迁移（EM）性能的结构和方法。一种方法包括形成互连，在互连上形成帽，并且在帽中形成多个孔以改善互连的电迁移性能。

48. 发明授权

US07572650B2 Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing 失效
标题翻译：局部金属沉淀形成的抑制和半导体加工中相应的金属化消耗
公开(公告)号：US07572650B2
公开(公告)日：2009-08-11
申请号：US11550853
申请日：2006-10-19
申请人： Jonathan D. Chapple-Sokol , Terence B. Hook , Baozhen Li , Thomas L. McDevitt , Christopher A. Ponsolle , Bette B. Reuter , Timothy D. Sullivan , Jeffrey S. Zimmerman
发明人： Jonathan D. Chapple-Sokol , Terence B. Hook , Baozhen Li , Thomas L. McDevitt , Christopher A. Ponsolle , Bette B. Reuter , Timothy D. Sullivan , Jeffrey S. Zimmerman
IPC分类号： H01L21/00
CPC分类号： H01L21/7684 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.
摘要翻译：用于抑制半导体加工中的局部金属沉淀形成（LMPF）的方法和结构。对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。可以在金属线周围形成监测斜坡端子并与金属线电断开。通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

49. 发明申请

US20090014884A1 SLOTS TO REDUCE ELECTROMIGRATION FAILURE IN BACK END OF LINE STRUCTURE 审中-公开
标题翻译：在线结构后端减少电气故障的缺点
公开(公告)号：US20090014884A1
公开(公告)日：2009-01-15
申请号：US11775914
申请日：2007-07-11
申请人： Baozhen Li
发明人： Baozhen Li
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/528 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A back-end of the line (BEOL) structure and method are disclosed. In one embodiment the BEOL structure may include: a copper line in an ultra low-k dielectric, the copper line connected on one end to a cathode via and on another end to an anode via; and a plurality of slots extending laterally along a length of the copper line, the plurality of slots being non-continuous along the length of the copper line, and wherein the plurality of slots reduce electromigration failure in the BEOL structure by enabling copper extrusions to occur along the plurality of slots.
摘要翻译：公开了一种后端（BEOL）结构和方法。在一个实施例中，BEOL结构可以包括：超低k电介质中的铜线，铜线在一端连接到阴极通孔，另一端连接到阳极通孔; 以及沿着铜线的长度横向延伸的多个槽，所述多个狭槽沿着铜线的长度是不连续的，并且其中所述多个狭槽通过使得铜挤压发生能够减小BEOL结构中的电迁移故障沿着多个槽。

50. 发明授权

US07087997B2 Copper to aluminum interlayer interconnect using stud and via liner 有权
公开(公告)号：US07087997B2
公开(公告)日：2006-08-08
申请号：US09805027
申请日：2001-03-12
申请人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
发明人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5226 , H01L23/53223 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

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